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1. 发明申请

US20070052041A1 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070052041A1
公开(公告)日：2007-03-08
申请号：US10558671
申请日：2004-05-31
申请人： Haruyuki Sorada , Takeshi Takagi , Akira Asai , Yoshihiko Kanzawa , Kouji Katayama , Junko Iwanaga
发明人： Haruyuki Sorada , Takeshi Takagi , Akira Asai , Yoshihiko Kanzawa , Kouji Katayama , Junko Iwanaga
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/78687
摘要： A semiconductor device according to this invention includes: a first insulating layer (11); a first body section (13) including an island-shaped semiconductor formed on the first insulating layer; a second body section (14) including an island-shaped semiconductor formed on the first insulating layer; a ridge-shaped connecting section (15) formed on the first insulating layer to interconnect the first body section and the second body section; a channel region (15a) formed by at least a part of the connecting section in lengthwise direction of the connecting section; a gate electrode (18) formed to cover a periphery of the channel region, with a second insulating layer intervening therebetween; a source region formed to extend over the first body section and a portion of the connecting section between the first body section and the channel region; and a drain region formed to extend over the second body section and a portion of the connecting section between the second body section and the channel region, wherein a semiconductor forming the channel region has a lattice strain.
摘要翻译：根据本发明的半导体器件包括：第一绝缘层（11）; 第一主体部分（13），其包括形成在所述第一绝缘层上的岛状半导体; 包括形成在所述第一绝缘层上的岛状半导体的第二主体部分（14）形成在第一绝缘层上以互连第一主体部分和第二主体部分的脊形连接部分（15）; 由所述连接部的至少一部分在所述连接部的长度方向上形成的通路区域（15a）形成为覆盖沟道区域的周边的栅极电极（18），其间插入有第二绝缘层; 形成为在第一主体部分上延伸的源极区域和在第一主体部分和沟道区域之间的连接部分的一部分; 以及形成为在第二主体部分上延伸的漏极区域和在第二主体部分和沟道区域之间的连接部分的一部分，其中形成沟道区域的半导体具有晶格应变。

2. 发明授权

US07473967B2 Strained channel finFET device 失效
标题翻译：应变通道finFET器件
公开(公告)号：US07473967B2
公开(公告)日：2009-01-06
申请号：US10558671
申请日：2004-05-31
申请人： Haruyuki Sorada , Takeshi Takagi , Akira Asai , Yoshihiko Kanzawa , Kouji Katayama , Junko Iwanaga
发明人： Haruyuki Sorada , Takeshi Takagi , Akira Asai , Yoshihiko Kanzawa , Kouji Katayama , Junko Iwanaga
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/78687
摘要： A semiconductor device according to this invention includes: a first insulating layer (11); a first body section (13) including an island-shaped semiconductor formed on the first insulating layer; a second body section (14) including an island-shaped semiconductor formed on the first insulating layer; a ridge-shaped connecting section (15) formed on the first insulating layer to interconnect the first body section and the second body section; a channel region (15a) formed by at least a part of the connecting section in lengthwise direction of the connecting section; a gate electrode (18) formed to cover a periphery of the channel region, with a second insulating layer intervening therebetween; a source region formed to extend over the first body section and a portion of the connecting section between the first body section and the channel region; and a drain region formed to extend over the second body section and a portion of the connecting section between the second body section and the channel region, wherein a semiconductor forming the channel region has a lattice strain.
摘要翻译：根据本发明的半导体器件包括：第一绝缘层（11）; 第一主体部分（13），其包括形成在所述第一绝缘层上的岛状半导体; 包括形成在所述第一绝缘层上的岛状半导体的第二主体部分（14）形成在第一绝缘层上以互连第一主体部分和第二主体部分的脊形连接部分（15）; 由连接部的长度方向的至少一部分形成的通道区域（15a）; 形成为覆盖沟道区域的周边的栅极电极（18），其间插入有第二绝缘层; 形成为在第一主体部分上延伸的源极区域和在第一主体部分和沟道区域之间的连接部分的一部分; 以及形成为在第二主体部分上延伸的漏极区域和在第二主体部分和沟道区域之间的连接部分的一部分，其中形成沟道区域的半导体具有晶格应变。

3. 发明授权

US08486788B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08486788B2
公开(公告)日：2013-07-16
申请号：US13162310
申请日：2011-06-16
申请人： Junko Iwanaga , Takeshi Takagi , Yoshihiko Kanzawa , Haruyuki Sorada , Tohru Saitoh , Takahiro Kawashima
发明人： Junko Iwanaga , Takeshi Takagi , Yoshihiko Kanzawa , Haruyuki Sorada , Tohru Saitoh , Takahiro Kawashima
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/823431 , H01L27/0886 , H01L29/66795
摘要： A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.
摘要翻译：一种半导体器件包括：形成沟槽的半导体衬底; 源极区域和漏极区域，每个源极区域和漏极区域被埋在沟槽中并且包含相同导电类型的杂质; 掩埋在沟槽中并设置在源区和漏区之间的半导体FIN; 设置在半导体FIN的侧表面上的栅极绝缘膜以及半导体FIN的上表面; 以及形成在栅极绝缘膜上的栅电极。

4. 发明申请

US20110244645A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110244645A1
公开(公告)日：2011-10-06
申请号：US13162310
申请日：2011-06-16
申请人： Junko IWANAGA , Takeshi Takagi , Yoshihiko Kanzawa , Haruyuki Sorada , Tohru Saitoh , Takahiro Kawashima
发明人： Junko IWANAGA , Takeshi Takagi , Yoshihiko Kanzawa , Haruyuki Sorada , Tohru Saitoh , Takahiro Kawashima
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/785 , H01L21/823431 , H01L27/0886 , H01L29/66795
摘要： A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.
摘要翻译：一种半导体器件包括：形成沟槽的半导体衬底; 源极区域和漏极区域，每个源极区域和漏极区域被埋在沟槽中并且包含相同导电类型的杂质; 掩埋在沟槽中并设置在源区和漏区之间的半导体FIN; 设置在半导体FIN的侧表面上的栅极绝缘膜以及半导体FIN的上表面; 以及形成在栅极绝缘膜上的栅电极。

5. 发明授权

US07986002B2 FINFET-type semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07986002B2
公开(公告)日：2011-07-26
申请号：US10549291
申请日：2004-03-19
申请人： Junko Iwanaga , Takeshi Takagi , Yoshihiko Kanzawa , Haruyuki Sorada , Tohru Saitoh , Takahiro Kawashima
发明人： Junko Iwanaga , Takeshi Takagi , Yoshihiko Kanzawa , Haruyuki Sorada , Tohru Saitoh , Takahiro Kawashima
IPC分类号： H01L29/66
CPC分类号： H01L29/785 , H01L21/823431 , H01L27/0886 , H01L29/66795
摘要： A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.
摘要翻译：一种半导体器件包括：形成沟槽的半导体衬底; 源极区域和漏极区域，每个源极区域和漏极区域被埋在沟槽中并且包含相同导电类型的杂质; 掩埋在沟槽中并设置在源区和漏区之间的半导体FIN; 设置在半导体FIN的侧表面上的栅极绝缘膜以及半导体FIN的上表面; 以及形成在栅极绝缘膜上的栅电极。

6. 发明申请

US20060208300A1 Finfet-type semiconductor device and method for fabricating the same 有权
标题翻译： Finfet型半导体器件及其制造方法
公开(公告)号：US20060208300A1
公开(公告)日：2006-09-21
申请号：US10549291
申请日：2004-03-19
申请人： Junko Iwanaga , Takeshi Takagi , Yoshihiko Kanzawa , Haruyuki Sorada , Tohru Saitoh , Takahiro Kawashima
发明人： Junko Iwanaga , Takeshi Takagi , Yoshihiko Kanzawa , Haruyuki Sorada , Tohru Saitoh , Takahiro Kawashima
IPC分类号： H01L27/108
CPC分类号： H01L29/785 , H01L21/823431 , H01L27/0886 , H01L29/66795
摘要： A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.
摘要翻译：一种半导体器件包括：形成沟槽的半导体衬底; 源极区域和漏极区域，每个源极区域和漏极区域被埋在沟槽中并且包含相同导电类型的杂质; 掩埋在沟槽中并设置在源区和漏区之间的半导体FIN; 设置在半导体FIN的侧表面上的栅极绝缘膜以及半导体FIN的上表面; 以及形成在栅极绝缘膜上的栅电极。

7. 发明授权

US07235830B2 Semiconductor device and process for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07235830B2
公开(公告)日：2007-06-26
申请号：US11260197
申请日：2005-10-28
申请人： Haruyuki Sorada , Takeshi Takagi , Akira Asai , Akira Inoue
发明人： Haruyuki Sorada , Takeshi Takagi , Akira Asai , Akira Inoue
IPC分类号： H01L29/76
CPC分类号： H01L29/78696 , H01L21/76264 , H01L21/76281 , H01L29/1054 , H01L29/66742 , H01L29/78687 , Y10S438/933 , Y10S438/938
摘要： The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3), the gate insulation film (10) and the gate electrode (11); wherein the first insulation film (13) overlies a part of the gate insulation film (10) surface. According to the semiconductor device, leakage current at the isolation edge can be suppressed and thus reliability can be improved.
摘要翻译：本发明提供一种半导体器件，包括：半导体层（3）; 经由栅极绝缘膜（10）形成在所述半导体层（3）上的栅电极（11）; 以及形成在所述半导体层（3），所述栅极绝缘膜（10）和所述栅电极（11）的侧壁的一个或多个的第一绝缘膜（13）。其中所述第一绝缘膜（13）覆盖所述栅极绝缘膜（10）表面的一部分。根据半导体装置，可以抑制隔离边缘处的漏电流，从而可以提高可靠性。

8. 发明申请

US20050040436A1 Semiconductor integrated circuit and fabrication method thereof 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US20050040436A1
公开(公告)日：2005-02-24
申请号：US10866093
申请日：2004-06-14
申请人： Haruyuki Sorada , Akira Asai , Takeshi Takagi , Akira Inoue , Yoshio Kawashima
发明人： Haruyuki Sorada , Akira Asai , Takeshi Takagi , Akira Inoue , Yoshio Kawashima
IPC分类号： H01L21/8238 , H01L27/10
CPC分类号： H01L21/823807
摘要： A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.
摘要翻译：根据本发明的半导体集成电路制造方法包括：通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤，由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管形成区域和一对第二装置形成区域。

9. 发明授权

US07564073B2 CMOS and HCMOS semiconductor integrated circuit 失效
标题翻译： CMOS和HCMOS半导体集成电路
公开(公告)号：US07564073B2
公开(公告)日：2009-07-21
申请号：US11294566
申请日：2005-12-06
申请人： Haruyuki Sorada , Akira Asai , Takeshi Takagi , Akira Inoue , Yoshio Kawashima
发明人： Haruyuki Sorada , Akira Asai , Takeshi Takagi , Akira Inoue , Yoshio Kawashima
IPC分类号： H01L27/04
CPC分类号： H01L21/823807
摘要： A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.
摘要翻译：根据本发明的半导体集成电路制造方法包括：通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤，由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管形成区域和一对第二装置形成区域。

10. 发明申请

US20060054944A1 Semiconductor device and process for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060054944A1
公开(公告)日：2006-03-16
申请号：US11260197
申请日：2005-10-28
申请人： Haruyuki Sorada , Takeshi Takagi , Akira Asai , Akira Inoue
发明人： Haruyuki Sorada , Takeshi Takagi , Akira Asai , Akira Inoue
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/78696 , H01L21/76264 , H01L21/76281 , H01L29/1054 , H01L29/66742 , H01L29/78687 , Y10S438/933 , Y10S438/938
摘要： The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3), the gate insulation film (10) and the gate electrode (11); wherein the first insulation film (13) overlies a part of the gate insulation film (10) surface. According to the semiconductor device, leakage current at the isolation edge can be suppressed and thus reliability can be improved.
摘要翻译：本发明提供一种半导体器件，包括：半导体层（3）; 经由栅极绝缘膜（10）形成在所述半导体层（3）上的栅电极（11）; 以及形成在所述半导体层（3），所述栅极绝缘膜（10）和所述栅电极（11）的侧壁的一个或多个的第一绝缘膜（13）。其中所述第一绝缘膜（13）覆盖所述栅极绝缘膜（10）表面的一部分。根据半导体装置，可以抑制隔离边缘处的漏电流，从而可以提高可靠性。

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