专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07227765B2 Content addressable memory cell 有权
标题翻译：内容可寻址存储单元
公开(公告)号：US07227765B2
公开(公告)日：2007-06-05
申请号：US10970842
申请日：2004-10-20
申请人： Guido De Sandre , Roberto Bez , Fabio Pellizzer
发明人： Guido De Sandre , Roberto Bez , Fabio Pellizzer
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C13/0004 , G11C14/00 , G11C14/009 , G11C15/046
摘要： A content addressable memory cell for a non-volatile content addressable memory, including a non-volatile storage element for storing a content digit, a selection input for selecting the memory cell, a search input for receiving a search digit, and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage element include at least one phase-change memory element for storing in a non-volatile way the respective content digit.
摘要翻译：一种用于非易失性内容可寻址存储器的内容可寻址存储器单元，包括用于存储内容数位的非易失性存储元件，用于选择存储单元的选择输入，用于接收搜索数字的搜索输入以及比较电路装置用于将搜索数字与内容数字进行比较，并用于驱动存储器单元的匹配输出，以便发出内容数字和搜索数字之间的匹配。非易失性存储元件包括用于以非易失性方式存储相应内容数字的至少一个相变存储器元件。

2. 发明申请

US20050062497A1 Field programmable gate array device 有权
标题翻译：现场可编程门阵列器件
公开(公告)号：US20050062497A1
公开(公告)日：2005-03-24
申请号：US10948079
申请日：2004-09-23
申请人： Fabio Pellizzer , Guido De Sandre , Roberto Bez
发明人： Fabio Pellizzer , Guido De Sandre , Roberto Bez
IPC分类号： G11C16/02 , G11C16/04 , H03K3/037 , H03K19/177
CPC分类号： G11C13/0004 , G11C16/0416 , H03K3/0375 , H03K19/1776
摘要： The present invention proposes a Field Programmable Gate Array device comprising a plurality of configurable electrical connections, a plurality of controlled switches, each one adapted to activating/de-activating at least one respective electrical connection in response to a switch control signal and a control unit including an arrangement of a plurality of control cells. Each control cells controls at least one of said controlled switches by the respective switch control signal, each control cell including a volatile storage element adapted to storing in a volatile way a control logic value corresponding to a preselected status of the at least one controlled switch, and providing to the controlled switch said switch control signal corresponding to the stored logic value. Each control cell further includes a non-volatile storage element coupled to the volatile storage element, the non-volatile storage element being adapted to storing in a non-volatile way the control logic value.
摘要翻译：本发明提出了一种现场可编程门阵列器件，其包括多个可配置的电连接，多个受控开关，每个控制开关适于响应于开关控制信号激活/去激活至少一个相应的电连接，控制单元包括多个控制单元的布置。每个控制单元通过相应的开关控制信号控制所述受控开关中的至少一个，每个控制单元包括易失性存储元件，其适于以易失性方式存储对应于至少一个受控开关的预选状态的控制逻辑值，以及向受控开关提供与所存储的逻辑值对应的所述开关控制信号。每个控制单元还包括耦合到易失性存储元件的非易失性存储元件，非易失性存储元件适于以非易失性方式存储控制逻辑值。

3. 发明授权

US07307451B2 Field programmable gate array device 有权
标题翻译：现场可编程门阵列器件
公开(公告)号：US07307451B2
公开(公告)日：2007-12-11
申请号：US10948079
申请日：2004-09-23
申请人： Fabio Pellizzer , Guido De Sandre , Roberto Bez
发明人： Fabio Pellizzer , Guido De Sandre , Roberto Bez
IPC分类号： H03K19/177 , G11C11/34
CPC分类号： G11C13/0004 , G11C16/0416 , H03K3/0375 , H03K19/1776
摘要： The present invention proposes a Field Programmable Gate Array device comprising a plurality of configurable electrical connections, a plurality of controlled switches, each one adapted to activating/de-activating at least one respective electrical connection in response to a switch control signal and a control unit including an arrangement of a plurality of control cells. Each control cells controls at least one of said controlled switches by the respective switch control signal, each control cell including a volatile storage element adapted to storing in a volatile way a control logic value corresponding to a preselected status of the at least one controlled switch, and providing to the controlled switch said switch control signal corresponding to the stored logic value. Each control cell further includes a non-volatile storage element coupled to the volatile storage element, the non-volatile storage element being adapted to storing in a non-volatile way the control logic value.
摘要翻译：本发明提出了一种现场可编程门阵列器件，其包括多个可配置的电连接，多个受控开关，每个控制开关适于响应于开关控制信号激活/去激活至少一个相应的电连接，控制单元包括多个控制单元的布置。每个控制单元通过相应的开关控制信号控制所述受控开关中的至少一个，每个控制单元包括易失性存储元件，其适于以易失性方式存储对应于至少一个受控开关的预选状态的控制逻辑值，以及向受控开关提供与所存储的逻辑值对应的所述开关控制信号。每个控制单元还包括耦合到易失性存储元件的非易失性存储元件，非易失性存储元件适于以非易失性方式存储控制逻辑值。

4. 发明申请

US20060018183A1 Content addressable memory cell 有权
标题翻译：内容可寻址存储单元
公开(公告)号：US20060018183A1
公开(公告)日：2006-01-26
申请号：US10970842
申请日：2004-10-20
申请人： Guido De Sandre , Roberto Bez , Fabio Pellizzer
发明人： Guido De Sandre , Roberto Bez , Fabio Pellizzer
IPC分类号： G11C8/02
CPC分类号： G11C15/04 , G11C13/0004 , G11C14/00 , G11C14/009 , G11C15/046
摘要： A content addressable memory cell for a non-volatile content addressable memory, including a non-volatile storage element for storing a content digit, a selection input for selecting the memory cell, a search input for receiving a search digit, and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage element include at least one phase-change memory element for storing in a non-volatile way the respective content digit.
摘要翻译：一种用于非易失性内容可寻址存储器的内容可寻址存储器单元，包括用于存储内容数位的非易失性存储元件，用于选择存储单元的选择输入，用于接收搜索数字的搜索输入以及比较电路装置用于将搜索数字与内容数字进行比较，并用于驱动存储器单元的匹配输出，以便发出内容数字和搜索数字之间的匹配。非易失性存储元件包括用于以非易失性方式存储相应内容数字的至少一个相变存储器元件。

5. 发明申请

US20100163833A1 ELECTRICAL FUSE DEVICE BASED ON A PHASE-CHANGE MEMORY ELEMENT AND CORRESPONDING PROGRAMMING METHOD 审中-公开
标题翻译：基于相变记忆元件的电保险丝装置和相应的编程方法
公开(公告)号：US20100163833A1
公开(公告)日：2010-07-01
申请号：US12347759
申请日：2008-12-31
申请人： Massimo Borghi , Guido De Sandre , Fabio Pellizzer , Innocenzo Tortorelli , Paola Zuliani
发明人： Massimo Borghi , Guido De Sandre , Fabio Pellizzer , Innocenzo Tortorelli , Paola Zuliani
IPC分类号： H01L45/00 , H01L21/44
CPC分类号： G11C17/16 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/79 , H01L23/5256 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1683 , H01L45/1691 , H01L2924/0002 , H01L2924/00
摘要： A fuse device has a fuse element provided with a first terminal and a second terminal and an electrically breakable region, which is arranged between the first terminal and the second terminal and is configured to undergo breaking as a result of the supply of a programming electrical quantity, thus electrically separating the first terminal from the second terminal. The electrically breakable region is of a phase-change material, in particular a chalcogenic material, for example GST.
摘要翻译：保险丝装置具有设置有第一端子和第二端子以及电气断开区域的熔丝元件，该区域设置在第一端子和第二端子之间，并且被配置为由于提供编程电量而导致断开从而将第一端子与第二端子电隔离。电致断裂区域是相变材料，特别是硫属材料，例如GST。

6. 发明申请

US20060226873A1 Level shifter translator 有权
公开(公告)号：US20060226873A1
公开(公告)日：2006-10-12
申请号：US11321732
申请日：2005-12-28
申请人： Guido De Sandre , Marco Poles , Marco Pasotti
发明人： Guido De Sandre , Marco Poles , Marco Pasotti
IPC分类号： H03K19/0175
CPC分类号： H03K19/018528 , H03K19/01707 , H03K19/01721
摘要： Level shifter translator of the type comprising at least one first transistor and one second MOS transistor belonging to respective circuit branches connected with a first common conduction terminal and connected towards a first potential reference and receiving, on the respective conduction terminals, input differential voltages, the first and the second transistor have respective circuit branches referring to a biasing circuit with current mirror, a third transistor allows to couple the second transistor to said biasing circuit, an inverter connected to an output of said the circuit with the output driving the third transistor.

7. 发明授权

US08264872B2 Column decoder for non-volatile memory devices, in particular of the phase-change type 有权
标题翻译：用于非易失性存储器件的列解码器，特别是相变型
公开(公告)号：US08264872B2
公开(公告)日：2012-09-11
申请号：US12548241
申请日：2009-08-26
申请人： Guido De Sandre , Marco Pasotti
发明人： Guido De Sandre , Marco Pasotti
IPC分类号： G11C11/00 , G11C8/10 , G11C7/00
CPC分类号： G11C13/0026 , G11C13/0004
摘要： A column decoder is for a phase-change memory device provided with an array of memory cells, a reading stage for reading data contained in the memory cells, and a programming stage for programming the data. The column decoder selects and enables biasing of a bitline of the array and generates a current path between the bitline and the reading stage or, alternatively, the programming stage, respectively during a reading or a programming operation of the contents of the memory cells. In the column decoder, a first decoder circuit generates a first current path between the bitline and the reading stage, and a second decoder circuit, distinct and separate from the first decoder circuit, generates a second current path, distinct from the first current path, between the bitline and the programming stage.
摘要翻译：列解码器用于设置有存储器单元阵列的相变存储器件，用于读取存储单元中包含的数据的读取级和用于对数据进行编程的编程级。列解码器选择并启用阵列的位线的偏置，并且在存储器单元的内容的读取或编程操作期间分别产生位线和读取级之间的电流路径，或者编程阶段。在列解码器中，第一解码器电路在位线和读取级之间产生第一电流路径，并且与第一解码器电路不同且分离的第二解码器电路产生与第一电流路径不同的第二电流路径，在位线和编程阶段之间。

8. 发明申请

US20100054032A1 ROW DECODER FOR NON-VOLATILE MEMORY DEVICES, IN PARTICULAR OF THE PHASE-CHANGE TYPE 有权
标题翻译：非易失性存储器件的ROW解码器，特别是相变型
公开(公告)号：US20100054032A1
公开(公告)日：2010-03-04
申请号：US12548246
申请日：2009-08-26
申请人： Guido De Sandre
发明人： Guido De Sandre
IPC分类号： G11C11/00 , G11C8/10 , G11C7/00
CPC分类号： G11C8/08 , G11C8/10 , G11C13/0004 , G11C13/0023 , G11C13/0028
摘要： A hierarchical row decoder is for a phase-change memory device provided with an array of memory cells organized according to a plurality of array wordlines and array bitlines. The row decoder has a global decoder that addresses first and a second global wordlines according to first address signals; and a local decoder, which is operatively coupled to the global decoder and addresses a respective array wordline according to the value the first and second global wordline and second address signals. The local decoder has a first circuit branch providing, when the first global wordline is addressed, a first current path between the array wordline and a first biasing source during a reading operation; and a second circuit branch providing, when the second global wordline is addressed, a second current path, distinct from the first current path, between the array wordline and a second biasing source during a programming operation.
摘要翻译：分层行解码器用于相变存储器件，该相变存储器件具有根据多个阵列字线和阵列位线组织的存储器单元阵列。行解码器具有根据第一地址信号寻址第一和第二全局字线的全局解码器; 以及本地解码器，其可操作地耦合到全局解码器，并且根据第一和第二全局字线和第二地址信号的值寻址相应的阵列字线。本地解码器具有第一电路分支，当第一全局字线被寻址时，提供在读取操作期间阵列字线和第一偏置源之间的第一电流路径; 以及第二电路分支，当在编程操作期间，当所述第二全局字线被寻址时，提供与所述第一电流路径不同的第二电流路径，所述第二电流路径在所述阵列字线和第二偏置源之间。

9. 发明申请

US20100020594A1 DEVICE FOR PROGRAMMING A PCM CELL WITH DISCHARGE OF CAPACITANCE AND METHOD FOR PROGRAMMING A PCM CELL 有权
标题翻译：用于编程具有放电容量的PCM单元的装置和用于编程PCM单元的方法
公开(公告)号：US20100020594A1
公开(公告)日：2010-01-28
申请号：US12510661
申请日：2009-07-28
申请人： Guido De Sandre , Luca Bettini
发明人： Guido De Sandre , Luca Bettini
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： A device for programming PCM cells includes a pulse-generator circuit for supplying programming current pulses. The pulse-generator circuit includes: at least one first capacitive element; a charging circuit, connectable to the first capacitive element in a first operating condition, for bringing a reference voltage on the first capacitive element to a reset value; a discharge-current generator, selectively connectable to the first capacitive element in a second operating condition, for discharging the first capacitive element through a controlled discharge current; a logic unit, configured to control connection and disconnection of the first capacitive element), of the charging circuit, and of the discharge-current generator; and a voltage-to-current converter, for converting the reference voltage into current.
摘要翻译：用于编程PCM单元的装置包括用于提供编程电流脉冲的脉冲发生器电路。脉冲发生器电路包括：至少一个第一电容元件; 充电电路，在第一操作状态下可连接到所述第一电容元件，用于使所述第一电容元件上的参考电压达到复位值; 放电电流发生器，在第二操作状态下可选择地连接到第一电容元件，用于通过受控放电电流对第一电容元件进行放电; 一个逻辑单元，被配置为控制第一电容元件的连接和断开）充电电路和放电电流发生器; 以及用于将参考电压转换为电流的电压 - 电流转换器。

10. 发明授权

US07504862B2 Level shifter translator 有权
标题翻译：电平移位器翻译器
公开(公告)号：US07504862B2
公开(公告)日：2009-03-17
申请号：US11321732
申请日：2005-12-28
申请人： Guido De Sandre , Marco Poles , Marco Pasotti
发明人： Guido De Sandre , Marco Poles , Marco Pasotti
IPC分类号： H03K19/0175
CPC分类号： H03K19/018528 , H03K19/01707 , H03K19/01721
摘要： Level shifter translator of the type comprising at least one first transistor and one second MOS transistor belonging to respective circuit branches connected with a first common conduction terminal and connected towards a first potential reference and receiving, on the respective conduction terminals, input differential voltages, the first and the second transistor have respective circuit branches referring to a biasing circuit with current mirror, a third transistor allows to couple the second transistor to said biasing circuit, an inverter connected to an output of said the circuit with the output driving the third transistor.
摘要翻译：该类型的电平移位器转换器包括至少一个第一晶体管和一个第二MOS晶体管，属于与第一公共导通端子连接并连接到第一电位基准的相应电路分支，并且在相应的导通端子上接收输入差分电压，第一晶体管和第二晶体管具有指向具有电流镜的偏置电路的各个电路分支，第三晶体管允许将第二晶体管耦合到所述偏置电路，反相器连接到所述电路的输出端，输出驱动第三晶体管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式