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1. 发明授权

US4195352A Split programmable logic array 失效
标题翻译：分割可编程逻辑阵列
公开(公告)号：US4195352A
公开(公告)日：1980-03-25
申请号：US814054
申请日：1977-07-08
申请人： George K. Tu , George E. Mager , Lamar T. Baker , Robert E. Markle
发明人： George K. Tu , George E. Mager , Lamar T. Baker , Robert E. Markle
IPC分类号： H03K19/177 , G06F9/00 , H03K19/08 , H03K19/34
CPC分类号： H03K19/17716
摘要： A mask programmable logic array (PLA) for producing a particular digital output given a certain digital input. The input signals to the PLA first pass through a series of AND gates resulting in a predetermined number of product terms being formed. The product signals then pass through a set of OR gates to become the final output signals. In the subject invention, the AND gates and OR gates are implemented through the use of NOR-NOR logic. A first set of NOR gates is implemented in an array to receive input signals and to produce product terms. A second and third set of NOR gates form two arrays. These two arrays are then located on either side of the first array to receive selected product signals in order to produce final output signals. In effect the OR portion of the PLA has been split into two arrays.TABLE OF CONTENTSSubjectBackground of the InventionSummary of the InventionBrief Description of the DrawingsDetailed Description of the Preferred EmbodimentThe System Block DiagramMicroprocessor Unit Pin DesignationsClock and Timing SignalsSystem TimingThe ROMThe Stack AreaThe RAM AreaElimination of Race Conditions in the RAMThe ALU and ControlTime Slot End PredictorThe CROMBit Manipulation SchemeData Pad Input/OutputPrecharged Data Line DriverBus ControlTest CircuitrySplit PLA ControlThe S-CounterDetails of Logic BlocksThe MOS/LSI ChipThe Chip Test FunctionsThe Instruction Set
摘要翻译：面罩可编程逻辑阵列（PLA），用于产生给定一定数字输入的特定数字输出。到PLA的输入信号首先通过一系列AND门，产生预定数量的产品项。然后，产品信号通过一组或门以成为最终的输出信号。在本发明中，AND门和OR门通过使用NOR-NOR逻辑来实现。第一组NOR门在阵列中实现以接收输入信号并产生产品术语。第二组和第三组NOR门形成两个阵列。然后，这两个阵列位于第一阵列的任一侧，以接收选定的产品信号，以产生最终的输出信号。实际上，PLA的OR部分已经分成两个阵列。

2. 发明授权

US4144561A Chip topography for MOS integrated circuitry microprocessor chip 失效
公开(公告)号：US4144561A
公开(公告)日：1979-03-13
申请号：US813902
申请日：1977-07-08
申请人： George K. Tu , Lamar T. Baker , Robert E. Markle , George E. Mager
发明人： George K. Tu , Lamar T. Baker , Robert E. Markle , George E. Mager
IPC分类号： G06F15/78 , H01L27/02 , G06F1/00 , G06F9/00
CPC分类号： H01L27/0207
摘要： The chip topography of an MOS microprocessor chip. The chip architecture includes an internal data bus and an internal address bus. Input/output circuitry is located along the top edge of the chip and is coupled to the data bus. Output circuitry is located along the bottom edge and coupled to the address bus. A program storage area which includes a ROM is located in the lower left hand corner of the chip. The ROM contains instruction words for defining the operation of the microprocessor. A data storage area which includes a RAM is located in the upper left hand corner of the chip and is coupled to the data bus. An ALU area is located to the right of the data storage area and is coupled to the data bus for performing arithmetic and logic operations on data. A condition decode ROM located in the approximate center of the chip is coupled to the data bus and is used for decoding a condition field of an instruction word received from the ROM. A bus control area is located in the upper right hand corner of the chip. A programmed control area is located between the ALU area and the bus control area in the upper right hand portion of the chip and is coupled to the data bus for receiving instruction words from the program storage area and for generating commands which define the operation of the microprocessor in response to the instruction words. A clock/T-counter is located in the lower right hand corner and is used for synchronizing data signal flow in the micrprocessor. A stack area is located in the lower right hand portion of the chip. Within this stack area are various registers located from top to bottom as follows; write X circuitry, an X register a stack array, stack read/write circuitry, a memory address register, and an incrementer. A stack control is located between the aforementioned stack circuitry and the right hand edge. In addition, a RAM decode is located between the RAM and the left hand edge, a ROM column decode is located between the ROM and the bottom edge, and a ROM row decode is located between the ROM and the stack area.

3. 发明授权

US4144589A Precharged data line driver 失效
标题翻译：预充电数据线驱动
公开(公告)号：US4144589A
公开(公告)日：1979-03-13
申请号：US813999
申请日：1977-07-08
申请人： Lamar T. Baker , George K. Tu
发明人： Lamar T. Baker , George K. Tu
IPC分类号： G11C11/4094 , G11C11/419 , G11C11/40
CPC分类号： G11C11/419 , G11C11/4094
摘要： For use in a microprocessor on a single semiconductor chip, circuitry responsive to a timing signal and a data signal for discharging a precharged data line to correspond to the data to be transmitted on the data line. First and second enhancement-type field effect devices are connected in series with the drain of the first device being connected to the data line and the source of the second device being connected to a source voltage. The gate of one of the field effect devices provides an input for the timing signal. The gate of the remaining field effect device provides an input for the data signal. A depletion-type field effect device has its source and gate coupled to the series connection point and its drain connected to a drain voltage source. The depletion-type field effect device prevents a charge redistribution from the data line to the series field effect devices when these devices are not discharging the line.
摘要翻译：用于在单个半导体芯片上的微处理器中，响应于定时信号的电路和用于对预先充电的数据线进行放电的数据信号以对应于要在数据线上发送的数据。第一和第二增强型场效应器件与第一器件的漏极串联连接到数据线，并且第二器件的源极连接到源极电压。场效应装置之一的门为定时信号提供输入。剩余场效应器件的栅极为数据信号提供输入。耗尽型场效应器件的源极和栅极耦合到串联连接点，其漏极连接到漏极电压源。耗尽型场效应器件当这些器件不放电时，防止从数据线到串联场效应器件的电荷再分配。

4. 发明授权

US3950709A Amplifier for random access computer memory 失效
标题翻译：用于随机存取计算机存储器的放大器
公开(公告)号：US3950709A
公开(公告)日：1976-04-13
申请号：US510981
申请日：1974-10-01
申请人： Richard B. Rubinstein , Lamar T. Baker
发明人： Richard B. Rubinstein , Lamar T. Baker
IPC分类号： G11C11/419 , G11C7/06 , G11C7/10 , H03K5/02 , H03F3/42
CPC分类号： G11C7/1069 , G11C7/06 , G11C7/1051 , H03K5/023
摘要： An integrated circuit ram amplifier includes a feedback loop which produces an output pulse before the output from the random access memory has completed its transition from full voltage to ground, thus increasing the computer's response time. The integrated circuit amplifier may find particular application in microprocessors (e.g. 8 bit word length, single bus two phase clock microprocessors).

5. 发明授权

US06299272B1 Pulse width modulation for correcting non-uniformity of acoustic inkjet printhead 有权
标题翻译：用于校正声学喷墨打印头的不均匀性的脉冲宽度调制
公开(公告)号：US06299272B1
公开(公告)日：2001-10-09
申请号：US09428823
申请日：1999-10-28
申请人： Lamar T. Baker , Steven A. Buhler , Abdul M. Elhatem , Scott A. Elrod , Babur B. Hadimioglu , Jaime Lerma , Mostafa R. Yazdy
发明人： Lamar T. Baker , Steven A. Buhler , Abdul M. Elhatem , Scott A. Elrod , Babur B. Hadimioglu , Jaime Lerma , Mostafa R. Yazdy
IPC分类号： B41J2938
CPC分类号： B41J2/04541 , B41J2/04573 , B41J2/04575 , B41J2/04588 , B41J2/04591 , B41J2/14008 , B41J2002/14322 , H03K5/05 , H03K7/08
摘要： An acoustic inkjet printhead utilizes a pulse width modulation to control droplet size or ejection velocity. An individual control pulse controls the duration and the time a RF signal is applied to each transducer. To modify the RF signal of each transducer, the pulse width of each control signal can be modified according to a predetermined correction data. The rising edge of the control data is delayed according to the correction data while the falling edge is kept the same.
摘要翻译：声学喷墨打印头利用脉冲宽度调制来控制液滴尺寸或喷射速度。单独的控制脉冲控制RF信号施加到每个换能器的持续时间和时间。为了修改每个换能器的RF信号，可以根据预定的校正数据来修改每个控制信号的脉冲宽度。当下降沿保持相同时，控制数据的上升沿根据校正数据被延迟。

6. 发明授权

US4156291A Circuitry for eliminating double ram row addressing 失效
标题翻译：消除双排行寻址的电路
公开(公告)号：US4156291A
公开(公告)日：1979-05-22
申请号：US814237
申请日：1977-07-08
申请人： Lamar T. Baker
发明人： Lamar T. Baker
IPC分类号： G11C11/418 , G11C7/00 , G11C8/00
CPC分类号： G11C11/418
摘要： Word select circuitry which eliminates double RAM row addressing is used with a read-write memory system of the type employing a plurality of word select lines. Sample and latch devices store input memory address data sampled at a predetermined rate. The devices provide at their outputs the stored data and its complement until new input memory address data is sampled. Additional circuitry is provided for producing a sampling signal which causes the latch devices to sample the input memory address data at the predetermined rate. A decoder provides signals to activate a selected one of the word select lines in response to the data signals received from the outputs of the latch devices. Additional circuitry is coupled to the decoder to produce a signal which precludes the activation of all of the word select lines when the latch devices are sampling input memory address data. In the preferred embodiment, all of the aforementioned circuitry is contained on a single semiconductor chip. In addition, a timing device on the chip is provided for synchronizing the data flow in the memory system.
摘要翻译：消除双RAM行寻址的字选择电路与采用多个字选择线的类型的读写存储器系统一起使用。采样和锁存装置存储以预定速率采样的输入存储器地址数据。这些设备在其输出端提供存储的数据及其补码，直到新的输入存储器地址数据被采样为止。提供附加电路用于产生采样信号，其使得锁存器件以预定速率对输入存储器地址数据进行采样。响应于从锁存装置的输出接收的数据信号，解码器提供信号以激活所选择的一个字选择线。附加电路耦合到解码器以产生当锁存器件正在对输入存储器地址数据进行采样时，排除所有字选择线的激活的信号。在优选实施例中，所有上述电路都包含在单个半导体芯片上。此外，芯片上的定时装置被提供用于使存储器系统中的数据流同步。

7. 发明授权

US06416163B1 Printhead array compensation device designs 有权
标题翻译：打印头阵列补偿装置设计
公开(公告)号：US06416163B1
公开(公告)日：2002-07-09
申请号：US09447316
申请日：1999-11-22
申请人： Abdul M. ElHatem , Lamar T. Baker , Jaime Lerma , Mostafa R. Yazdy
发明人： Abdul M. ElHatem , Lamar T. Baker , Jaime Lerma , Mostafa R. Yazdy
IPC分类号： B41J2135
CPC分类号： B41J2/04575 , B41J2/04541 , B41J2/04543 , B41J2202/13
摘要： Described are various compensation circuit designs to ensure proper shutoff of an unselected transducer in a transducer switching matrix. The switch of an unselected transducer is moved to a strong OFF state by injection of a compensation current. The compensation network is implemented as semiconductor integrated circuits which provide a high-voltage column switching diode, and a compensation switch. The compensation switch and column switching diode are configured such that they are isolated from each other.
摘要翻译：描述了各种补偿电路设计，以确保在换能器开关矩阵中正确地切断未选择的换能器。未选择的换能器的开关通过注入补偿电流而移动到强关闭状态。补偿网络实现为提供高压列开关二极管和补偿开关的半导体集成电路。补偿开关和列开关二极管被配置为使得它们彼此隔离。

8. 发明授权

US4196357A Time slot end predictor 失效
标题翻译：时隙结束预测器
公开(公告)号：US4196357A
公开(公告)日：1980-04-01
申请号：US814064
申请日：1977-07-08
申请人： Lamar T. Baker
发明人： Lamar T. Baker
IPC分类号： G06F1/10 , H03K13/34 , H03K5/15 , H03K17/16 , H03K19/08
CPC分类号： G06F1/10
摘要： For use in a microprocessor on a single semiconductor chip, a circuit responsive to first and second non-overlapping time signals for removing timed delay in a first data line. A first enhancement-type field effect device has its drain coupled to the first data line and its gate providing an input for the first timing signal. A second enhancement-type field effect device has its drain coupled to the source of the first device and its source coupled to a source voltage. The source voltage is at ground potential. A third enhancement field effect device has its drain coupled to the first data line, its source coupled to the gate of the second device, and its gate providing an input for the second timing signal.
摘要翻译：为了在单个半导体芯片上的微处理器中使用响应于第一和第二非重叠时间信号的电路，用于消除第一数据线中的定时延迟。第一增强型场效应器件的漏极耦合到第一数据线，其栅极提供用于第一定时信号的输入。第二增强型场效应器件的漏极耦合到第一器件的源极，其源极耦合到源极电压。源电压处于地电位。第三增强场效应器件的漏极耦合到第一数据线，其源极耦合到第二器件的栅极，并且其栅极为第二定时信号提供输入。

9. 发明授权

US4133611A Two-page interweaved random access memory configuration 失效
标题翻译：两页交织随机存取存储器配置
公开(公告)号：US4133611A
公开(公告)日：1979-01-09
申请号：US813991
申请日：1977-07-08
申请人： Lamar T. Baker
发明人： Lamar T. Baker
IPC分类号： G11C11/412 , G11C11/417 , H03K19/0185 , H03K19/0944 , G11C7/00 , G11C11/40
CPC分类号： H03K19/018557 , G11C11/412 , G11C11/417 , H03K19/09443 , Y10S257/923
摘要： A random access memory (RAM) containing 256 memory cells organized as two pages, each page containing 16 8-bit wide working registers. RAM row address circuitry as well as read-write and page-select circuitry are provided. A fixed transistor static RAM cell is used as the memory cell. Double rail transfer of data is employed. The memory cells and bit lines associated with each of the two pages is interweaved in the array so that the precharged circuitry and the RAM input/output circuitry associated with each of the pages is alternately configured on the chip.TABLE OF CONTENTSSubjectBackground of the InventionSummary of the InventionBrief Description of the DrawingsDetailed Description of the Preferred EmbodimentThe System Block DiagramMicroprocessor Unit Pin DesignationsClock and Timing SignalsSystem TimingThe ROMThe Stack AreaThe RAM AreaElimination of Race Conditions in the RAMThe ALU and ControlTime Slot End PredictorPrecharged Data Line Driver
摘要翻译：一个包含256个存储单元的随机存取存储器（RAM）组成两页，每页包含16个8位宽的工作寄存器。提供RAM行地址电路以及读写和页选电路。使用固定晶体管静态RAM单元作为存储单元。采用双轨传输数据。与两个页面中的每一页相关联的存储器单元和位线被交织在阵列中，使得与芯片中的每个页面相关联的预充电电路和RAM输入/输出电路交替配置。

10. 发明授权

US4101788A MOS buffer circuit 失效
公开(公告)号：US4101788A
公开(公告)日：1978-07-18
申请号：US779122
申请日：1977-03-18
申请人： Lamar T. Baker
发明人： Lamar T. Baker
IPC分类号： H03K5/02 , H03K19/0185 , H03K19/096 , H03K19/08 , H03K19/34 , H03K19/36 , H03K19/40
CPC分类号： H03K5/023 , H03K19/018507 , H03K19/096
摘要： A MOS control circuit for controlling an output signal, said control circuit being coupled to first and second sources of potential. The magnitude or peak-to-peak amplitude of the first source of potential is greater than the magnitude developed by the second source of potential. The control circuit output signal has a waveshape magnitude of desired dimension somewhere between the magnitude of the second source of potential and the magnitude of the first source of potential. In order to accomplish this, a first inverter receives and inverts an input signal and produces an output potential at a node. A clamping circuit reduces the potential at the node by a desired amount. A source follower is driven by the potential at the node and also receives the input signal. The output of the source follower is the control output signal.

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