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1. 发明授权

US07465986B2 Power semiconductor device including insulated source electrodes inside trenches 有权
标题翻译：功率半导体器件包括沟槽内的绝缘源电极
公开(公告)号：US07465986B2
公开(公告)日：2008-12-16
申请号：US11211268
申请日：2005-08-25
申请人： Dev Alok Girdhar , Ling Ma , Steven T. Peake , David Paul Jones
发明人： Dev Alok Girdhar , Ling Ma , Steven T. Peake , David Paul Jones
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/7805 , H01L29/7806 , H01L29/861
摘要： A power semiconductor device includes a plurality of trenches formed within a semiconductor body, each trench including one or more electrodes formed therein. In particular, according to embodiments of the invention, the plurality of trenches of a semiconductor device may include one or more gate electrodes, may include one or more gate electrodes or one or more source electrodes, or may include a combination of both gate and source electrodes formed therein. The trenches and electrodes may have varying depths within the semiconductor body.
摘要翻译：功率半导体器件包括形成在半导体本体内的多个沟槽，每个沟槽包括形成在其中的一个或多个电极。具体地，根据本发明的实施例，半导体器件的多个沟槽可以包括一个或多个栅电极，可以包括一个或多个栅电极或一个或多个源电极，或者可以包括栅极和源极的组合电极形成在其中。沟槽和电极在半导体本体内可能具有不同的深度。

2. 发明授权

US07998808B2 Semiconductor device fabrication using spacers 有权
标题翻译：使用间隔物的半导体器件制造
公开(公告)号：US07998808B2
公开(公告)日：2011-08-16
申请号：US12409077
申请日：2009-03-23
申请人： Vijay Viswanathan , Dev Alok Girdhar , Timothy Henson , David Paul Jones
发明人： Vijay Viswanathan , Dev Alok Girdhar , Timothy Henson , David Paul Jones
IPC分类号： H01L21/8242 , H01L21/20 , H01L21/76
CPC分类号： H01L29/7813 , H01L21/2815 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/66734
摘要： A process for fabrication of a semiconductor device that includes forming a first trench in a semiconductor body, forming spaced spacers in the first trench, and forming a narrower second trench at the bottom of the first trench using the spacers as a mask.
摘要翻译：一种制造半导体器件的方法，包括在半导体本体中形成第一沟槽，在第一沟槽中形成间隔开的间隔物，并且使用间隔物作为掩模，在第一沟槽的底部形成较窄的第二沟槽。

3. 发明申请

US20090263952A1 SEMICONDUCTOR DEVICE FABRICATION USING SPACERS 有权
标题翻译：半导体器件制造使用间隔
公开(公告)号：US20090263952A1
公开(公告)日：2009-10-22
申请号：US12409077
申请日：2009-03-23
申请人： Vijay Viswanathan , Dev Alok Girdhar , Timothy Henson , David Paul Jones
发明人： Vijay Viswanathan , Dev Alok Girdhar , Timothy Henson , David Paul Jones
IPC分类号： H01L21/44
CPC分类号： H01L29/7813 , H01L21/2815 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/66734
摘要： A process for fabrication of a semiconductor device that includes forming a first trench in a semiconductor body, forming spaced spacers in the first trench, and forming a narrower second trench at the bottom of the first trench using the spacers as a mask.
摘要翻译：一种半导体器件的制造方法，其包括在半导体本体中形成第一沟槽，在第一沟槽中形成间隔开的间隔物，并且使用间隔物作为掩模，在第一沟槽的底部形成较窄的第二沟槽。

4. 发明授权

US08647971B2 Method of manufacturing junction barrier schottky diode with dual silicides 有权
标题翻译：制造具有双重硅化物的结型肖特基二极管的方法
公开(公告)号：US08647971B2
公开(公告)日：2014-02-11
申请号：US13356624
申请日：2012-01-23
申请人： Dev Alok Girdhar , Michael David Church , Alexander Kalnitsky
发明人： Dev Alok Girdhar , Michael David Church , Alexander Kalnitsky
IPC分类号： H01L21/28 , H01L21/44
CPC分类号： H01L29/872 , H01L27/0629 , H01L29/456 , H01L29/47 , H01L29/7833
摘要： An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.
摘要翻译：包括结势垒肖特基二极管的集成电路具有N型阱，阱表面中的P型阳极区域和阱表面中的N型肖特基区域，并且水平地邻接阳极区域。第一硅化物层在肖特基区域上并与其相邻的阳极区域形成肖特基接触。与第一硅化物不同的第二硅化物层位于阳极区上。对阳极区域和阱的第二硅化物进行欧姆接触。

5. 发明申请

US20100314708A1 JUNCTION BARRIER SCHOTTKY DIODE 失效
标题翻译： JUNCTION BARRIER肖特基二极管
公开(公告)号：US20100314708A1
公开(公告)日：2010-12-16
申请号：US12868346
申请日：2010-08-25
申请人： Dev Alok Girdhar , Michael David Church
发明人： Dev Alok Girdhar , Michael David Church
IPC分类号： H01L29/872
CPC分类号： H01L29/66143 , H01L27/0629 , H01L29/063 , H01L29/0692 , H01L29/872
摘要： A junction barrier Schottky diode has an N-type well having a surface and a first peak impurity concentration; a P-type anode region in the surface of the well, and having a second peak impurity concentration; an N-type cathode contact region in the surface of the well and laterally spaced from a first wall of the anode region, and having a third peak impurity concentration; and a first N-type region in the surface of the well and laterally spaced from a second wall of the anode region, and having a fourth impurity concentration. The center of the spaced region between the first N-type region and the second wall of the anode region has a fifth peak impurity concentration. An ohmic contact is made to the anode region and cathode contact region, and a Schottky contact is made to the first N-type region. The first and fifth peak impurity concentrations are less than the fourth peak impurity concentration, and the fourth peak impurity concentration is less that the second and third peak impurity concentrations.
摘要翻译：接合势垒肖特基二极管具有具有表面和第一峰值杂质浓度的N型阱; 阱的表面中的P型阳极区，具有第二峰杂质浓度; 在所述阱的表面中的N型阴极接触区域，并且与所述阳极区域的第一壁横向间隔开，并且具有第三峰值杂质浓度; 以及在所述阱的表面中的第一N型区域，并且与所述阳极区域的第二壁横向间隔开，并且具有第四杂质浓度。阳极区域的第一N型区域和第二壁之间的间隔区域的中心具有第五峰值杂质浓度。对阳极区域和阴极接触区域进行欧姆接触，并且对第一N型区域进行肖特基接触。第一和第五峰杂质浓度小于第四峰杂质浓度，第四峰杂质浓度小于第二和第三峰杂质浓度。

6. 发明申请

US20090096019A1 MOSGATED POWER SEMICONDUCTOR DEVICE WITH SOURCE FIELD ELECTRODE 有权
标题翻译：具有源极场效应晶体管功率半导体器件
公开(公告)号：US20090096019A1
公开(公告)日：2009-04-16
申请号：US12243253
申请日：2008-10-01
申请人： Dev Alok Girdhar , Timothy Donald Henson
发明人： Dev Alok Girdhar , Timothy Donald Henson
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/76
摘要： A power semiconductor device which includes a source field electrode, and at least one insulated gate electrode adjacent a respective side of the source field electrode, the source field electrode and the gate electrode being disposed in a common trench.
摘要翻译：一种功率半导体器件，其包括源极电极和与源极场电极的相应侧相邻的至少一个绝缘栅电极，源极场电极和栅电极设置在公共沟槽中。

7. 发明授权

US08492225B2 Integrated trench guarded schottky diode compatible with powerdie, structure and method 有权
标题翻译：集成沟槽保护肖特基二极管兼容电源，结构和方法
公开(公告)号：US08492225B2
公开(公告)日：2013-07-23
申请号：US12938589
申请日：2010-11-03
申请人： Dev Alok Girdhar , Francois Hebert
发明人： Dev Alok Girdhar , Francois Hebert
IPC分类号： H01L21/336
CPC分类号： H01L27/0629 , H01L27/088 , H01L29/4236 , H01L29/66621 , H01L29/7834 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a voltage converter including a trench field effect transistor (FET) and a trench guarded Schottky diode which is integrated with the trench FET. In an embodiment, a voltage converter can include a lateral FET, a trench FET, and a trench guarded Schottky diode integrated with the trench FET. A method to form a voltage converter can include the formation of a trench FET gate, a trench guarded Schottky diode gate, and a lateral FET gate using a single conductive layer such as a polysilicon layer.
摘要翻译：一种电压转换器的方法和结构，包括与沟槽FET集成的沟槽场效应晶体管（FET）和沟槽保护肖特基二极管。在一个实施例中，电压转换器可以包括横向FET，沟槽FET和与沟槽FET集成的沟槽保护肖特基二极管。形成电压转换器的方法可以包括使用诸如多晶硅层的单个导电层形成沟槽FET栅极，沟槽保护肖特基二极管栅极和横向FET栅极。

8. 发明申请

US20120122308A1 METHOD OF MANUFACTURING JUNCTION BARRIER SCHOTTKY DIODE WITH DUAL SILICIDES 有权
标题翻译：制造双晶硅二极管肖特基二极管的方法
公开(公告)号：US20120122308A1
公开(公告)日：2012-05-17
申请号：US13356624
申请日：2012-01-23
申请人： Dev Alok Girdhar , Michael David Church , Alexander Kalnitsky
发明人： Dev Alok Girdhar , Michael David Church , Alexander Kalnitsky
IPC分类号： H01L21/8222
CPC分类号： H01L29/872 , H01L27/0629 , H01L29/456 , H01L29/47 , H01L29/7833
摘要： An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.
摘要翻译：包括结势垒肖特基二极管的集成电路具有N型阱，阱表面中的P型阳极区域和阱表面中的N型肖特基区域，并且水平地邻接阳极区域。第一硅化物层在肖特基区域上并与其相邻的阳极区域形成肖特基接触。与第一硅化物不同的第二硅化物层位于阳极区上。对阳极区域和阱的第二硅化物进行欧姆接触。

9. 发明申请

US20110121387A1 INTEGRATED GUARDED SCHOTTKY DIODE COMPATIBLE WITH TRENCH-GATE DMOS, STRUCTURE AND METHOD 审中-公开
标题翻译：集成的保护肖特基二极管与TRENCH-GATE DMOS兼容，结构和方法
公开(公告)号：US20110121387A1
公开(公告)日：2011-05-26
申请号：US12770074
申请日：2010-04-29
申请人： Francois Hebert , Dev Alok Girdhar
发明人： Francois Hebert , Dev Alok Girdhar
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66727 , H01L29/1095 , H01L29/41766 , H01L29/4238 , H01L29/456 , H01L29/47 , H01L29/66734 , H01L29/7806 , H01L29/872
摘要： A plurality of transistor cells, each of which can include a transistor P-body region and a Schottky diode, wherein the transistor P-body region can be formed below the Schottky diode to provide a semiconductor device having desirable electrical characteristics.
摘要翻译：多个晶体管单元，其中每个晶体管单元可以包括晶体管P体区域和肖特基二极管，其中晶体管P体区域可以形成在肖特基二极管下方，以提供具有所需电气特性的半导体器件。

10. 发明授权

US07750426B2 Junction barrier Schottky diode with dual silicides 失效
标题翻译：具有双重硅化物的结型势垒肖特基二极管
公开(公告)号：US07750426B2
公开(公告)日：2010-07-06
申请号：US11849565
申请日：2007-09-04
申请人： Dev Alok Girdhar , Michael David Church , Alexander Kalnitsky
发明人： Dev Alok Girdhar , Michael David Church , Alexander Kalnitsky
IPC分类号： H01L27/095 , H01L29/47 , H01L31/07
CPC分类号： H01L29/872 , H01L27/0629 , H01L29/456 , H01L29/47 , H01L29/7833
摘要： An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.
摘要翻译：包括结势垒肖特基二极管的集成电路具有N型阱，阱表面中的P型阳极区域和阱表面中的N型肖特基区域，并且水平地邻接阳极区域。第一硅化物层在肖特基区域上并与其相邻的阳极区域形成肖特基接触。与第一硅化物不同的第二硅化物层位于阳极区上。对阳极区域和阱的第二硅化物进行欧姆接触。

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