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    • 6. 发明授权
    • Plateline driver with RAMP rate control
    • 具有RAMP速率控制的Plateline驱动程序
    • US07349237B2
    • 2008-03-25
    • US11003707
    • 2004-12-03
    • Sung-Wei LinSudhir K. MadanJohn Fong
    • Sung-Wei LinSudhir K. MadanJohn Fong
    • G11C11/00G11C5/14
    • H03K19/00346H03K19/185
    • A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). A first conductor (710, 850) is coupled to a plurality of the rows (702, 704, and 706) of memory cells. A first transistor (810) has a current path coupled between a voltage supply terminal (800) and the first conductor (850) and a control terminal coupled to receive a first control signal (PLV). A second transistor (820) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).
    • 公开了一种减少字线耦合的存储电路和方法。 电路包括排列成行(702,704和706)和列(750,752)的多个存储单元。 第一导体(710,850)耦合到存储器单元的多个行(702,704和706)。 第一晶体管(810)具有耦合在电压源端子(800)和第一导体(850)之间的电流通路和耦合以接收第一控制信号(PLV)的控制端子。 第二晶体管(820)具有耦合在电压供应端和第一导体之间的电流路径,以及耦合以接收第二控制信号(PLW)的控制端。
    • 8. 发明授权
    • Low resistance plate line bus architecture
    • 低电阻板线总线架构
    • US07443708B2
    • 2008-10-28
    • US11409628
    • 2006-04-24
    • Sudhir Kumar MadanSung-Wei LinJohn Fong
    • Sudhir Kumar MadanSung-Wei LinJohn Fong
    • G11C11/22
    • G11C11/22H01L27/11502
    • An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.
    • 描述了其中板线在字线方向上延伸的FeRAM存储器阵列,其在具有公共板线连接的阵列中提供减小的板线电阻。 下板线电阻降低了板线上负尖峰的幅度,以减少FeCap去极化的可能性。 多列存储器单元的两条或多条板条沿位线方向互连。 一个或多个虚拟存储器单元列的一些或全部平板线也可互连,以减小板线电阻并且最小化阵列的有源单元的位线电容的任何增加。 改进的FeRAM阵列提供了降低的数据错误率,特别是在快速的存储周期时间。
    • 10. 发明申请
    • Set associative repair cache systems and methods
    • 设置关联修复缓存系统和方法
    • US20060080572A1
    • 2006-04-13
    • US11231001
    • 2005-09-20
    • John Fong
    • John Fong
    • G06F11/00
    • G11C29/808
    • The present invention facilitates scaling of memory devices and operation thereof by employing a set associative repair cache system to correct or repair identified faulty memory cells. A repair cache region router 602 compares a repair region portion of a memory address to repair cache regions to identify a matching repair cache region. Then, a local repair location router 603 compares a repair address portion of the memory address to a local repair location addresses particular to the matching repair cache region to identify a matching local repair address. If a matching local repair address is identified, a repair component 606 provides access to a repair data location according to the matching local repair address and the matching repair cache region. Otherwise, a main memory 604 provides access to a memory location according to the memory address. Other systems and methods are disclosed.
    • 本发明通过采用一组关联修复缓存系统来校正或修复所识别的故障存储器单元,便于存储器件的缩放及其操作。 修复高速缓存区域路由器602将存储器地址的修复区域部分与修复高速缓存区域进行比较,以识别匹配的修复高速缓存区域。 然后,本地修复位置路由器603将存储器地址的修复地址部分与匹配修复高速缓存区域特定的本地修复位置地址进行比较,以识别匹配的本地修复地址。 如果识别出匹配的本地修复地址,则修复组件606根据匹配的本地修复地址和匹配修复高速缓存区域提供对修复数据位置的访问。 否则,主存储器604根据存储器地址提供对存储器位置的访问。 公开了其它系统和方法。