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1. 发明授权

US06242303B1 Nonvolatile memories with high capacitive-coupling ratio 有权
标题翻译：具有高电容耦合比的非易失性存储器
公开(公告)号：US06242303B1
公开(公告)日：2001-06-05
申请号：US09440138
申请日：1999-11-15
申请人： Ling-Sung Wang , Chia-Chen Liu
发明人： Ling-Sung Wang , Chia-Chen Liu
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/11558
摘要： A method for manufacturing an erasable programmable memory is disclosed, and an enlargement of the coupling area between control and floating gates is employed to increase the capacitive-coupling ratio. Firstly, the isolation regions are formed on the substrate. A polysilicon layer is formed on a portion of the control region of the substrate to form an uneven silicon surface. An ion implantation is carried out to form the doped tunnel region and the control gate. A tunnel oxide layer and a non-tunnel oxide layer are formed on the doped tunnel region, and an inter-poly dielectric is formed on the control gate. A floating gate is now deposited on the doped tunnel region and the control gate. Then an inter-layer dielectric is formed and etched to provide the isolation and connect between control gate and interconnects.
摘要翻译：公开了一种用于制造可擦除可编程存储器的方法，并且采用控制和浮置栅极之间的耦合区域的放大来增加电容耦合比。首先，在基板上形成隔离区域。在基板的控制区域的一部分上形成多晶硅层，形成不均匀的硅表面。进行离子注入以形成掺杂的隧道区域和控制栅极。在掺杂隧道区域上形成隧道氧化物层和非隧道氧化物层，并且在控制栅极上形成多晶硅电介质。浮置栅极现在沉积在掺杂的隧道区域和控制栅极上。然后形成并蚀刻层间电介质以提供控制栅极和互连之间的隔离和连接。

2. 发明授权

US06255164B1 EPROM cell structure and a method for forming the EPROM cell structure 有权
标题翻译： EPROM单元结构和形成EPROM单元结构的方法
公开(公告)号：US06255164B1
公开(公告)日：2001-07-03
申请号：US09365732
申请日：1999-08-03
申请人： Chia-Chen Liu , Ling-Sung Wang
发明人： Chia-Chen Liu , Ling-Sung Wang
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： The present invention provides a cell structure of an electrically programmable read only memory (EPROM) which includes an EPROM gate structure, a source junction region, a drain junction region, a first dielectric layer, a self-aligned common source line, a self-aligned drain contact, a second dielectric layer, and a conductive line. The EPROM gate structure is on a portion of the substrate. The source junction region is in the substrate located on a first lateral side, namely the left side in the figure, of the EPROM gate structure. The drain junction region is in the substrate located on a second lateral side, namely the right side in the figure, of the EPROM gate structure. The first dielectric layer covers on top and sidewalls of the EPROM gate structure. The self-aligned common source line neighbors the first dielectric layer and is above the substrate on a portion of the source junction region. The self-aligned drain contact neighbors the first dielectric layer, and is above the substrate on a portion of the drain junction region. The second dielectric layer covers the first dielectric layer, the self-aligned common source line, and the self-aligned drain contact. The conductive line is on the second dielectric layer and communicates to the self-aligned drain contact.
摘要翻译：本发明提供一种电可编程只读存储器（EPROM）的单元结构，其包括EPROM栅极结构，源极结，漏极结区，第一介电层，自对准共源源极线，排列的漏极接触，第二介电层和导电线。 EPROM门结构位于衬底的一部分上。源极结区位于EPROM栅极结构的位于第一侧面（即图中左侧）的衬底中。漏极结区域位于EPROM栅极结构的位于第二侧面（即，图中右侧）的衬底中。第一介电层覆盖在EPROM门结构的顶部和侧壁上。自对准的公共源极线邻近第一电介质层，并且在源极结部分的一部分上方的衬底上方。自对准漏极接触器邻近第一介电层，并且在漏极结区域的一部分上方的衬底上方。第二电介质层覆盖第一介电层，自对准公共源极线和自对准漏极接触。导线在第二电介质层上并与自对准漏极接触连通。

3. 发明授权

US08513143B2 Semiconductor structure and method of manufacturing 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US08513143B2
公开(公告)日：2013-08-20
申请号：US13212469
申请日：2011-08-18
申请人： Mei-Hsuan Lin , Chih-Hsun Lin , Chih-Kang Chao , Ling-Sung Wang
发明人： Mei-Hsuan Lin , Chih-Hsun Lin , Chih-Kang Chao , Ling-Sung Wang
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L23/481 , H01L21/76802 , H01L21/76822 , H01L21/76825 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L2924/0002 , H01L2924/00
摘要： The present application discloses a method of manufacturing a semiconductor structure. According to at least one embodiment, a first etch stop layer is formed over a conductive feature and a substrate, and the conductive feature is positioned over the substrate. A second etch stop layer is formed over the first etch stop layer. A first etch is performed to form an opening in the second etch stop layer, and the opening exposes a portion of the first etch stop layer. A second etch is performed to extend the opening downwardly by removing a portion of the exposed first etch stop layer, and the extended opening exposes a portion of the conductive feature.
摘要翻译：本申请公开了一种制造半导体结构的方法。根据至少一个实施例，在导电特征和衬底之上形成第一蚀刻停止层，并且导电特征位于衬底上。在第一蚀刻停止层上形成第二蚀刻停止层。执行第一蚀刻以在第二蚀刻停止层中形成开口，并且开口暴露第一蚀刻停止层的一部分。执行第二蚀刻以通过去除暴露的第一蚀刻停止层的一部分向下延伸开口，并且延伸的开口暴露导电特征的一部分。

4. 发明申请

US20130207166A1 Methods and Apparatus for Doped SiGe Source/Drain Stressor Deposition 有权
标题翻译：掺杂SiGe源/漏极应力沉积的方法和装置
公开(公告)号：US20130207166A1
公开(公告)日：2013-08-15
申请号：US13371177
申请日：2012-02-10
申请人： Chao-Hsuing Chen , Ling-Sung Wang , Chi-Yen Lin
发明人： Chao-Hsuing Chen , Ling-Sung Wang , Chi-Yen Lin
IPC分类号： H01L29/772 , H01L21/20
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0257 , H01L21/02579 , H01L21/02639 , H01L29/0847 , H01L29/167 , H01L29/66628 , H01L29/66636
摘要： A semiconductor device system, structure and method of manufacture of a source/drain with SiGe stressor material to address effects due to dopant out-diffusion are disclosed. In an embodiment, a semiconductor substrate is provided with a gate structure, and recesses for source and drain are formed on opposing sides of the gate structure. Doped stressors are embedded into the recessed source and drain regions, and a plurality of layers of undoped stressor, lightly doped stressor, highly doped stressor, and a cap layer are formed in an in-situ epitaxial process. In another embodiment the doped stressor material is boron doped epitaxial SiGe. In an alternative embodiment an additional layer of undoped stressor material is formed.
摘要翻译：公开了一种利用SiGe应力材料制造源极/漏极的半导体器件系统，结构和方法，以解决由掺杂剂扩散引起的影响。在一个实施例中，半导体衬底设置有栅极结构，并且用于源极和漏极的凹槽形成在栅极结构的相对侧上。掺杂的应力源嵌入到凹陷的源极和漏极区域中，并且在原位外延工艺中形成多层未掺杂的应力源，轻掺杂应力源，高掺杂应力源和覆盖层。在另一个实施例中，掺杂应力源材料是硼掺杂的外延SiGe。在替代实施例中，形成附加的未掺杂应力源材料层。

5. 发明授权

US08468474B2 Reducing metal pits through optical proximity correction 有权
标题翻译：通过光学邻近校正减少金属凹坑
公开(公告)号：US08468474B2
公开(公告)日：2013-06-18
申请号：US13618045
申请日：2012-09-14
申请人： Jiun-Jie Huang , Chi-Yen Lin , Ling-Sung Wang
发明人： Jiun-Jie Huang , Chi-Yen Lin , Ling-Sung Wang
IPC分类号： G06F17/50
CPC分类号： H01L21/76838 , H01L23/528 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A method includes retrieving first layouts of an integrated circuit from a non-transitory computer-readable medium. The first layouts include a via pattern in a via layer, and a metal line pattern in a metal layer immediately over the via layer. The metal line pattern has an enclosure to the via pattern. The enclosure is increased to a second enclosure to generate second layouts of the integrated circuit.
摘要翻译：一种方法包括从非暂时计算机可读介质检索集成电路的第一布局。第一布局包括通孔层中的通孔图案，以及在通孔层上方的金属层中的金属线图案。金属线图案具有到通孔图案的外壳。外壳增加到第二个外壳以产生集成电路的第二布局。

6. 发明授权

US07473986B2 Positive-intrinsic-negative (PIN) diode semiconductor devices and fabrication methods thereof 有权
标题翻译：正本征负（PIN）二极管半导体器件及其制造方法
公开(公告)号：US07473986B2
公开(公告)日：2009-01-06
申请号：US11563814
申请日：2006-11-28
申请人： Kern-Huat Ang , Ling-Sung Wang
发明人： Kern-Huat Ang , Ling-Sung Wang
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L27/1021 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and fabrication methods thereof. A first dielectric layer with a first conductor line along a first direction is disposed on a semiconductor substrate, wherein the top surface of the first conductor line is lower than the top surface of the first dielectric layer. A second dielectric layer comprising an opening corresponding to the first diode element is disposed on the first dielectric layer. A semiconductor diode component comprises a first diode element disposed on the first conductor line, wherein the top surface of the first diode element is level with the top surface of the first dielectric layer; and a second diode element and a third diode element are filled in the opening.
摘要翻译：半导体器件及其制造方法。具有沿着第一方向具有第一导体线的第一电介质层设置在半导体衬底上，其中第一导体线的顶表面比第一电介质层的顶表面低。包括对应于第一二极管元件的开口的第二电介质层设置在第一电介质层上。半导体二极管部件包括设置在第一导体线上的第一二极管元件，其中第一二极管元件的顶表面与第一介电层的顶表面平齐; 并且第二二极管元件和第三二极管元件填充在开口中。

7. 发明授权

US06524909B1 Self-aligned fabricating process and structure of source line of etox flash memory 有权
标题翻译：自动对准制造工艺和etox闪存源线结构
公开(公告)号：US06524909B1
公开(公告)日：2003-02-25
申请号：US09494524
申请日：2000-01-31
申请人： Ling-Sung Wang , Jyh-Ren Wu
发明人： Ling-Sung Wang , Jyh-Ren Wu
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/28273
摘要： A self-aligned fabricating process and a structure of ETOX flash memory. A plurality of parallel lines for device isolation is formed in a substrate, and then forming a plurality of parallel stacked gates above the substrate. The device isolation lines and the stacked gates are perpendicular to each other. A plurality of first insulation layers is formed such that an insulation layer is formed over each stacked gate. Spacers are also formed over the sidewalls of each stacked gate. A plurality of source arrays and drain arrays are formed in the substrate between neighboring stacked gates. The source and drain arrays are parallel to the stacked gates, with a source array and a drain array formed in alternating positions between the stacked gates. Each source array comprises a plurality of source-doped regions located between the device isolation lines respectively. Similarly, each drain array has a plurality of drain-doped regions located between the device isolation lines. A plurality of source lines is formed in the space between neighboring spacers above the source array.
摘要翻译：自对准制造工艺和ETOX闪存的结构。在衬底中形成用于器件隔离的多条平行线，然后在衬底上形成多个平行的堆叠栅极。器件隔离线和堆叠栅极彼此垂直。形成多个第一绝缘层，使得在每个堆叠的栅极上形成绝缘层。隔板也形成在每个堆叠门的侧壁上。在相邻堆叠栅极之间的衬底中形成多个源极阵列和漏极阵列。源极和漏极阵列平行于堆叠栅极，源极阵列和漏极阵列形成在堆叠栅极之间的交替位置。每个源极阵列分别包括位于器件隔离线之间的多个源极掺杂区域。类似地，每个漏极阵列具有位于器件隔离线之间的多个漏极掺杂区域。在源阵列上方的相邻间隔物之间的空间中形成多条源极线。

8. 发明授权

US06245667B1 Method of forming via 失效
标题翻译：形成通孔的方法
公开(公告)号：US06245667B1
公开(公告)日：2001-06-12
申请号：US09465905
申请日：1999-12-17
申请人： Ling-Sung Wang , Chingfu Lin , Chien-Jung Wang
发明人： Ling-Sung Wang , Chingfu Lin , Chien-Jung Wang
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a via. A stacked structure has a barrier layer and a metal line is formed over a substrate. Spacers capable of serving as a barrier are formed over tapering sidewalls of the stacked structure before vias and plugs are formed.
摘要翻译：形成通孔的方法。堆叠结构具有阻挡层，并且在衬底上形成金属线。在形成通孔和插塞之前，可以在堆叠结构的锥形侧壁上形成能够用作屏障的间隔物。

9. 发明授权

US6146946A Method of fabricating a flash memory 有权
标题翻译：制造闪速存储器的方法
公开(公告)号：US6146946A
公开(公告)日：2000-11-14
申请号：US417393
申请日：1999-10-13
申请人： Ling-Sung Wang , Jyh-Ren Wu
发明人： Ling-Sung Wang , Jyh-Ren Wu
IPC分类号： H01L21/28 , H01L29/423 , H01L29/51 , H01L21/336
CPC分类号： H01L29/511 , H01L21/28273 , H01L29/42324
摘要： The invention describes a method of fabricating an integrated circuit used to prevent undercutting of an oxide layer due to wet etching. A semiconductor substrate has a gate formed thereon. A conformal oxide layer is formed to cover the gate. Then, a nitrogen ion implantation process is performed to introduce nitrogen ions into the surface of the conformal oxide layer. A high temperature thermal oxidation is performed in order to form Si--N bonds, that is, the nitrogen ions bonding with the silicon atoms of the conformal oxide layer, or to form Si--ON bonds, that is, the nitrogen ions bonding with the oxygen atoms of the conformal oxide layer. A dielectric layer, which covers the conformal oxide layer, is formed. Thereafter, the dielectric layer is etched back to form spacers on the sidewalls of the gate. A wet etching process is performed to remove a part of the conformal oxide layer exposed by the spacers.
摘要翻译：本发明描述了一种制造集成电路的方法，该集成电路用于防止由于湿蚀刻而导致的氧化层的底切。半导体衬底具有形成在其上的栅极。形成保形氧化物层以覆盖栅极。然后，进行氮离子注入工艺以将氮离子引入保形氧化物层的表面。进行高温热氧化以形成Si-N键，即与保形氧化物层的硅原子结合的氮离子，或者形成Si-ON键，即氮离子与保形氧化物层的氧原子。形成覆盖保形氧化物层的电介质层。此后，电介质层被回蚀以在栅极的侧壁上形成间隔物。执行湿蚀刻工艺以去除由间隔物暴露的一部分共形氧化物层。

10. 发明授权

US6026028A Hot carrier injection programming and negative gate voltage channel erase flash EEPROM structure 失效
标题翻译：热载波注入编程和负栅极电压通道擦除闪存EEPROM结构
公开(公告)号：US6026028A
公开(公告)日：2000-02-15
申请号：US123305
申请日：1998-07-28
申请人： Chen-Hsi Lin , Chih-Ming Chen , Ling-Sung Wang , Horng-Ming Lee , Ko-Hsing Chang
发明人： Chen-Hsi Lin , Chih-Ming Chen , Ling-Sung Wang , Horng-Ming Lee , Ko-Hsing Chang
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： H01L29/7885
摘要： A flash electrical erasable programmable read only memory structure that utilizes hot carrier injection for programming and negative gate voltage to carry out channel erase operations. Characteristic of the memory structure includes a triple well structure having a P-well and an N-well located within a P-type substrate, wherein the N-well isolated the P-well from the P-type substrate. Therefore, an independently isolated triple well structure is established during memory erase operation.
摘要翻译：闪存电可擦除可编程只读存储器结构，其利用热载流子注入用于编程和负栅极电压来执行通道擦除操作。存储器结构的特征包括具有P阱和位于P型衬底内的N阱的三阱结构，其中N阱从P型衬底隔离P阱。因此，在存储器擦除操作期间建立独立隔离的三重阱结构。

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