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1. 发明申请

US20120126308A1 NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20120126308A1
公开(公告)日：2012-05-24
申请号：US13298591
申请日：2011-11-17
申请人： Beom Yong KIM , Kwon HONG , Kee Jeung LEE , Ki Hong LEE
发明人： Beom Yong KIM , Kwon HONG , Kee Jeung LEE , Ki Hong LEE
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11524 , G11C16/14 , G11C16/28 , H01L27/11556 , H01L27/1157 , H01L27/11582
摘要： A non-volatile memory device includes a plurality of memory cells stacked along a channel protruded from a substrate, a first select transistor connected to one end of the plurality of memory cells, a first interlayer dielectric layer for being coupled between a source line and the first select transistor, and a second interlayer dielectric layer disposed between the first select transistor and the one end of the plurality of memory cells, and configured to include a first recess region.
摘要翻译：非易失性存储器件包括沿着从衬底突出的通道堆叠的多个存储器单元，连接到多个存储器单元的一端的第一选择晶体管，用于耦合在源极线与源极之间的第一层间电介质层第一选择晶体管和设置在第一选择晶体管和多个存储单元的一端之间的第二层间电介质层，并且被配置为包括第一凹部区域。

2. 发明申请

US20120146127A1 NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20120146127A1
公开(公告)日：2012-06-14
申请号：US13403065
申请日：2012-02-23
申请人： Ki-Hong LEE , Kwon HONG , Dae-Gyu SHIN
发明人： Ki-Hong LEE , Kwon HONG , Dae-Gyu SHIN
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： A nonvolatile memory device includes a pipe gate having a pipe channel hole; a plurality of interlayer insulation layers and a plurality of gate electrodes alternately stacked over the pipe gate; a pair of columnar cell channels passing through the interlayer insulation layers and the gate electrodes and coupling a pipe channel formed in the pile channel hole; a first blocking layer and a charge trapping and charge storage layer formed on sidewalk of the columnar cell channels; and a second blocking layer formed between the first blocking layer and the plurality of gate electrodes.
摘要翻译：非易失性存储装置包括具有管道通道孔的管道浇口; 多个层间绝缘层和交替层叠在管栅上的多个栅电极; 一对穿过层间绝缘层和栅电极的柱状电池通道，并且耦合形成在通道孔中的管道; 在柱状细胞通道的人行道上形成的第一阻挡层和电荷俘获和电荷存储层; 以及形成在第一阻挡层和多个栅电极之间的第二阻挡层。

3. 发明申请

US20100163963A1 NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20100163963A1
公开(公告)日：2010-07-01
申请号：US12493820
申请日：2009-06-29
申请人： Ki-Hong LEE , Kwon HONG
发明人： Ki-Hong LEE , Kwon HONG
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/7881 , H01L29/42324 , H01L29/4234 , H01L29/792
摘要： There is provided a nonvolatile memory device having a tunnel dielectric layer formed over a substrate, the charge capturing layer formed over the tunnel dielectric layer and including a combination of at least one charge storage layer and at least one charge trap layer, a charge blocking layer formed over the charge capturing layer, and a gate electrode formed over the charge blocking layer.
摘要翻译：提供了一种非易失性存储器件，其具有在衬底上形成的隧道介电层，所述电荷俘获层形成在所述隧道介电层上并且包括至少一个电荷存储层和至少一个电荷俘获层，电荷阻挡层形成在电荷捕获层上，以及形成在电荷阻挡层上的栅电极。

4. 发明申请

US20070278561A1 FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：闪存存储器件及其制造方法
公开(公告)号：US20070278561A1
公开(公告)日：2007-12-06
申请号：US11751013
申请日：2007-05-19
申请人： Kwon HONG , Eun Shil Park , Min Sik Jang
发明人： Kwon HONG , Eun Shil Park , Min Sik Jang
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L29/513 , H01L29/7881
摘要： A non-volatile memory device has a gate dielectric film formed between a floating gate and a control gate. The gate dielectric film is formed by forming an oxide film and a ZrO2/Al2O3/ZrO2 (ZAZ) film. Accordingly, the reliability of non-volatile memory devices can be improved while securing a high coupling ratio.
摘要翻译：非易失性存储器件具有形成在浮置栅极和控制栅极之间的栅极电介质膜。栅电介质膜通过形成氧化物膜和ZrO 2 / Al 2 O 3 / ZrO 2 2 / （ZAZ）电影。因此，可以在确保高耦合比的同时提高非易失性存储器件的可靠性。

5. 发明申请

US20100062581A1 METHOD OF FABRICATING NON-VOLATILE MEMORY DEVICE 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20100062581A1
公开(公告)日：2010-03-11
申请号：US12432187
申请日：2009-04-29
申请人： Jung-Woo PARK , Jin-Ki JUNG , Kwon HONG , Ki-Seon PARK
发明人： Jung-Woo PARK , Jin-Ki JUNG , Kwon HONG , Ki-Seon PARK
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： H01L27/11519 , H01L27/11521
摘要： Provided is a method of fabricating a non-volatile semiconductor device. The method includes: forming a first hard mask layer over a substrate; etching the first hard mask layer and the substrate to form a plurality of isolation trenches extending in parallel to one another in a first direction; burying a dielectric layer in the isolation trenches to form a isolation layer; forming a plurality of floating gate mask patterns extending in parallel to one another in a second direction intersecting with the first direction over a resulting structure where the isolation layer is formed; etching the first hard mask layer by using the floating gate mask patterns as an etch barrier to form a plurality of island-shaped floating gate electrode trenches; and burying a conductive layer in the floating gate electrode trenches to form a plurality of island-shaped floating gate electrodes.
摘要翻译：提供了制造非易失性半导体器件的方法。该方法包括：在衬底上形成第一硬掩模层; 蚀刻第一硬掩模层和衬底以形成在第一方向上彼此平行延伸的多个隔离沟槽; 在隔离沟槽中埋置介电层以形成隔离层; 在形成所述隔离层的结果上形成在与所述第一方向相交的第二方向上彼此平行延伸的多个浮置栅极掩模图案; 通过使用浮栅掩模图案作为蚀刻势垒来蚀刻第一硬掩模层，以形成多个岛状浮栅电极沟槽; 并在所述浮栅电极沟槽中埋设导电层以形成多个岛状浮栅。

6. 发明申请

US20110068380A1 SEMICONDUCTOR DEVICE WITH BULB-TYPE RECESSED CHANNEL AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有BULB类型的通道的半导体器件及其制造方法
公开(公告)号：US20110068380A1
公开(公告)日：2011-03-24
申请号：US12953255
申请日：2010-11-23
申请人： Yong-Soo KIM , Hong-Seon YANG , Se-Aug JANG , Seung-Ho PYI , Kwon HONG , Heung-Jae CHO , Kwan-Yong LIM , Min-Gyu SUNG , Seung-Ryong LEE , Tae-Yoon KIM
发明人： Yong-Soo KIM , Hong-Seon YANG , Se-Aug JANG , Seung-Ho PYI , Kwon HONG , Heung-Jae CHO , Kwan-Yong LIM , Min-Gyu SUNG , Seung-Ryong LEE , Tae-Yoon KIM
IPC分类号： H01L29/772
CPC分类号： H01L29/66553 , H01L27/10876 , H01L29/518 , H01L29/66621
摘要： A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.
摘要翻译：一种制造半导体器件的方法，包括提供具有灯泡型凹陷区域的衬底，在灯泡型凹陷区域上形成栅极绝缘层和衬底，并在栅极绝缘层上形成栅极导电层。栅极导电层填充灯泡型凹陷区域。栅极导电层包括两个或多个导电层和导电层之间的不连续界面。

7. 发明申请

US20080233762A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080233762A1
公开(公告)日：2008-09-25
申请号：US11950220
申请日：2007-12-04
申请人： Kwon HONG
发明人： Kwon HONG
IPC分类号： H01L21/469
CPC分类号： H01L21/31645 , C23C16/405 , C23C16/45531 , C23C16/45553 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02194 , H01L21/022 , H01L21/0228 , H01L21/3141 , H01L21/3142 , H01L21/3162 , H01L21/31641 , H01L28/40
摘要： A method of manufacturing a semiconductor device includes forming a high dielectric insulating layer. An amorphous high dielectric insulating layer having a high density is formed by using a precursor which can be deposited through the atomic layer deposition method at a temperature above 400° C. A resulting insulating exhibits a reduced crystallization during a subsequent annealing process. The capacitance equivalent thickness (CET) characteristic and the leakage current characteristic are improved.
摘要翻译：制造半导体器件的方法包括形成高介电绝缘层。通过使用可以通过原子层沉积法在高于400℃的温度下沉积的前体形成具有高密度的非晶高介电绝缘层。所得到的绝缘体在随后的退火过程中表现出减少的结晶。提高了电容当量厚度（CET）特性和漏电流特性。

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