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1. 发明授权

US09123545B2 Semiconductor device with single-event latch-up prevention circuitry 有权
标题翻译：具有单事件闩锁防止电路的半导体器件
公开(公告)号：US09123545B2
公开(公告)日：2015-09-01
申请号：US14188461
申请日：2014-02-24
申请人： Jianan Yang , James D. Burnett , Brad J. Garni , Thomas W. Liston
发明人： Jianan Yang , James D. Burnett , Brad J. Garni , Thomas W. Liston
IPC分类号： H01L29/66 , H01L27/06 , H01L27/092
CPC分类号： H01L27/06 , H01L27/0921
摘要： A semiconductor device includes a parasitic silicon-controlled rectifier (SCR) and a first transistor. The parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The first transistor is coupled between a first power supply node and an emitter of the parasitic pnp BJT. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp BJT following a single-event latch-up (SEL) event.
摘要翻译：半导体器件包括寄生硅可控整流器（SCR）和第一晶体管。寄生SCR包括寄生pnp双极结型晶体管（BJT）和寄生npn BJT。第一晶体管耦合在第一电源节点和寄生pnp BJT的发射极之间。第一晶体管包括耦合到第一电源节点的第一端子，耦合到寄生pnp BJT的发射极的第二端子和控制端子。第一晶体管不位于pnp BJT的基极和第一电源节点之间。在单事件闩锁（SEL）事件之后，第一晶体管限制由寄生pnp BJT传导的电流。

2. 发明授权

US09026808B2 Memory with word level power gating 有权
标题翻译：内存字级电源门控
公开(公告)号：US09026808B2
公开(公告)日：2015-05-05
申请号：US13457248
申请日：2012-04-26
申请人： Jianan Yang , Mark W. Jetton , Thomas W. Liston
发明人： Jianan Yang , Mark W. Jetton , Thomas W. Liston
IPC分类号： G06F1/26 , G06F1/32 , G06F12/00 , G11C8/08 , G11C11/418
CPC分类号： G11C11/418 , G11C8/08
摘要： In accordance with at least one embodiment, memory power gating at word level is provided. In accordance with at least one embodiment, a word level power-gating technique, which is enabled by adding an extra control bit to each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.) of a memory array, provides fine-grained power reduction for a memory array. In accordance with at least one embodiment, a gating transistor is provided for each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.).
摘要翻译：根据至少一个实施例，提供了字级的存储器电源门控。根据至少一个实施例，通过向每个子阵列（例如，每个字，每行，每个字线，每个位线，阵列的每个部分等）添加额外的控制位来实现的字电平门控技术。）存储器阵列，为存储器阵列提供细粒度的功率降低。根据至少一个实施例，为每个子阵列（例如，每个字，每行，每个字线，每个位线，阵列的每个部分等）提供门控晶体管。

3. 发明授权

US08685800B2 Single event latch-up prevention techniques for a semiconductor device 有权
标题翻译：半导体器件的单事件闭锁预防技术
公开(公告)号：US08685800B2
公开(公告)日：2014-04-01
申请号：US13560010
申请日：2012-07-27
申请人： Jianan Yang , James D. Burnett , Brad J. Garni , Thomas W. Liston , Huy Van Pham
发明人： Jianan Yang , James D. Burnett , Brad J. Garni , Thomas W. Liston , Huy Van Pham
IPC分类号： H01L21/332
CPC分类号： H01L27/06 , H01L27/0921
摘要： A technique for addressing single-event latch-up (SEL) in a semiconductor device includes determining a location of a parasitic silicon-controlled rectifier (SCR) in an integrated circuit design of the semiconductor device. In this case, the parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The technique also includes incorporating a first transistor between a first power supply node and an emitter of the parasitic pnp BJT in the integrated circuit design. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp bipolar junction transistor following an SEL.
摘要翻译：用于在半导体器件中寻址单事件闩锁（SEL）的技术包括在半导体器件的集成电路设计中确定寄生硅控整流器（SCR）的位置。在这种情况下，寄生SCR包括寄生pnp双极结型晶体管（BJT）和寄生npnBJT。该技术还包括在集成电路设计中在第一电源节点和寄生pnp BJT的发射极之间并入第一晶体管。第一晶体管包括耦合到第一电源节点的第一端子，耦合到寄生pnp BJT的发射极的第二端子和控制端子。第一晶体管不位于pnp BJT的基极和第一电源节点之间。第一晶体管限制了在SEL之后由寄生pnp双极结晶体传导的电流。

4. 发明申请

US20130290750A1 MEMORY WITH WORD LEVEL POWER GATING 有权
标题翻译：记忆与词水平功率增益
公开(公告)号：US20130290750A1
公开(公告)日：2013-10-31
申请号：US13457248
申请日：2012-04-26
申请人： Jianan Yang , Mark W. Jetton , Thomas W. Liston
发明人： Jianan Yang , Mark W. Jetton , Thomas W. Liston
IPC分类号： G06F1/32 , G06F1/00
CPC分类号： G11C11/418 , G11C8/08
摘要： In accordance with at least one embodiment, memory power gating at word level is provided. In accordance with at least one embodiment, a word level power-gating technique, which is enabled by adding an extra control bit to each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.) of a memory array, provides fine-grained power reduction for a memory array. In accordance with at least one embodiment, a gating transistor is provided for each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.).
摘要翻译：根据至少一个实施例，提供了字级的存储器电源门控。根据至少一个实施例，通过向每个子阵列（例如，每个字，每行，每个字线，每个位线，阵列的每个部分等）添加额外的控制位来实现的字电平门控技术。）存储器阵列，为存储器阵列提供细粒度的功率降低。根据至少一个实施例，为每个子阵列（例如，每个字，每行，每个字线，每个位线，阵列的每个部分等）提供门控晶体管。

5. 发明申请

US20100232202A1 DUAL PORT MEMORY DEVICE 有权
标题翻译：双端口存储器件
公开(公告)号：US20100232202A1
公开(公告)日：2010-09-16
申请号：US12404892
申请日：2009-03-16
申请人： Olga R. Lu , Lawrence F. Childs , Thomas W. Liston
发明人： Olga R. Lu , Lawrence F. Childs , Thomas W. Liston
IPC分类号： G11C5/06 , G11C8/16 , G11C8/00
CPC分类号： G11C8/16 , G11C8/10 , G11C11/412 , G11C11/413 , G11C11/419
摘要： A multi-port memory device having a storage node, a precharge node, a first, second, third, and fourth transistor, and a control module. The first transistor includes a current electrode connected to the storage node, another current electrode connected to a first bit line, and a gate connected to a first wordline. The second transistor includes a current electrode connected to the storage node, another current electrode connected to a second bit line, and a gate connected to a second wordline. The third transistor includes a current electrode connected to the reference node, another current electrode connected to the first bit line, and a gate. The fourth transistor includes a current electrode connected to the precharge node, another current electrode connected to the second bit line, and a gate. The control module deactivates the fourth transistor in response to a dummy access of the first storage module at the second transistor.
摘要翻译：一种具有存储节点，预充电节点，第一，第二，第三和第四晶体管以及控制模块的多端口存储器件。第一晶体管包括连接到存储节点的电流电极，连接到第一位线的另一电流电极和连接到第一字线的栅极。第二晶体管包括连接到存储节点的电流电极，连接到第二位线的另一个电流电极和连接到第二字线的栅极。第三晶体管包括连接到参考节点的电流电极，连接到第一位线的另一电流电极和栅极。第四晶体管包括连接到预充电节点的电流电极，连接到第二位线的另一电流电极和栅极。响应于在第二晶体管处的第一存储模块的虚拟访问，控制模块停用第四晶体管。

6. 发明授权

US07554841B2 Circuit for storing information in an integrated circuit and method therefor 有权
标题翻译：用于在集成电路中存储信息的电路及其方法
公开(公告)号：US07554841B2
公开(公告)日：2009-06-30
申请号：US11534715
申请日：2006-09-25
申请人： Thomas W. Liston
发明人： Thomas W. Liston
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A circuit has a storing portion, a write portion and a read portion. In one embodiment, read portion has a transistor which has a substantially thinner gate oxide than the transistors in the storing portion and the transistors in the write portion. In an alternate embodiment, circuit has a plurality of read ports. In an alternate embodiment, selecting the optimal gate oxide thickness for the transistors in circuit allows the trade-off between transistor switching speed and gate leakage current to be optimized to produce a circuit having a fast enough read access time and a low enough standby power.
摘要翻译：电路具有存储部分，写入部分和读取部分。在一个实施例中，读取部分具有晶体管，其具有比存储部分中的晶体管和写入部分中的晶体管更薄的栅极氧化物。在替代实施例中，电路具有多个读端口。在替代实施例中，为电路中的晶体管选择最佳栅极氧化物厚度允许优化晶体管切换速度和栅极泄漏电流之间的折衷，以产生具有足够快的读取访问时间和足够低的待机功率的电路。

7. 发明授权

US07706207B2 Memory with level shifting word line driver and method thereof 有权
标题翻译：具有电平转换字线驱动器的存储器及其方法
公开(公告)号：US07706207B2
公开(公告)日：2010-04-27
申请号：US12209477
申请日：2008-09-12
申请人： Thomas W. Liston , Shahnaz P. Chowdhury-Nagle , Perry H. Pelley, III
发明人： Thomas W. Liston , Shahnaz P. Chowdhury-Nagle , Perry H. Pelley, III
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C5/144 , G11C8/10
摘要： A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.
摘要翻译：存储器包括包括多个字线的位单元阵列和具有提供预解码值的输出的地址解码电路。地址解码电路包括具有第一栅极氧化物厚度的第一多个晶体管。存储器还包括字线驱动器电路，其具有耦合到地址解码电路的输出的输入和多个输出，每个输出耦合到多个字线中的相应字线。字线驱动器包括具有大于第一栅极氧化物厚度的第二栅极氧化物厚度的第二多个晶体管。还提供了一种操作存储器的方法。

8. 发明授权

US09317087B2 Memory column drowsy control 有权
标题翻译：内存列困倦控制
公开(公告)号：US09317087B2
公开(公告)日：2016-04-19
申请号：US13689331
申请日：2012-11-29
申请人： Ravindraraj Ramaraju , Jianan Yang , Mark W. Jetton , Thomas W. Liston , George P. Hoekstra , Andrew C. Russell
发明人： Ravindraraj Ramaraju , Jianan Yang , Mark W. Jetton , Thomas W. Liston , George P. Hoekstra , Andrew C. Russell
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F1/3296 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column.
摘要翻译：根据至少一个实施例，提供列级功率控制粒度以使用昏迷列控制位来控制存储器的低功率状态，以控制单个列级的低功率状态，以保护存储器免于弱位故障。根据至少一个实施例，提供了在存储器阵列中使用专用行位单元的方法，其中行中的每个位控制阵列中相应列的低功率状态。使用特殊的控制信号来访问字线，字线在常规字线地址空间之外。提供了一种机制来指定弱位列，并设置与该特定列相对应的控制位以禁用该列的困倦/低功率状态。

9. 发明授权

US08766703B1 Method and apparatus for sensing on-chip characteristics 有权
标题翻译：用于感测片上特性的方法和装置
公开(公告)号：US08766703B1
公开(公告)日：2014-07-01
申请号：US13835690
申请日：2013-03-15
申请人： Jianan Yang , James D. Burnett , Mark W. Jetton , Thomas W. Liston
发明人： Jianan Yang , James D. Burnett , Mark W. Jetton , Thomas W. Liston
IPC分类号： H01L35/00 , G05F1/567
CPC分类号： G05F1/567 , G01K7/01 , G01R31/2884 , H01L22/34
摘要： A sensor circuit performs a method for sensing on-chip characteristics. The method includes generating a first voltage using a drive current through a first set of transistors that are operating in saturation mode and generating a second voltage using subthreshold leakage current from a second set of transistors that are in subthreshold mode. The method further includes comparing the second voltage to the first voltage to sense an on-chip characteristic. The sensed on-chip characteristic can be temperature and/or gate length variation.
摘要翻译：传感器电路执行用于检测片上特性的方法。该方法包括利用在饱和模式下工作的第一组晶体管的驱动电流产生第一电压，并使用来自处于亚阈值模式的第二组晶体管的亚阈值泄漏电流产生第二电压。该方法还包括将第二电压与第一电压进行比较以感测片上特性。感测到的片上特性可以是温度和/或栅极长度变化。

10. 发明授权

US07940599B2 Dual port memory device 有权
标题翻译：双端口存储设备
公开(公告)号：US07940599B2
公开(公告)日：2011-05-10
申请号：US12404892
申请日：2009-03-16
申请人： Olga R. Lu , Lawrence F. Childs , Thomas W. Liston
发明人： Olga R. Lu , Lawrence F. Childs , Thomas W. Liston
IPC分类号： G11C7/00 , G11C7/10 , G11C8/00
CPC分类号： G11C8/16 , G11C8/10 , G11C11/412 , G11C11/413 , G11C11/419
摘要： A multi-port memory device having a storage node, a precharge node, a first, second, third, and fourth transistor, and a control module. The first transistor includes a current electrode connected to the storage node, another current electrode connected to a first bit line, and a gate connected to a first wordline. The second transistor includes a current electrode connected to the storage node, another current electrode connected to a second bit line, and a gate connected to a second wordline. The third transistor includes a current electrode connected to the reference node, another current electrode connected to the first bit line, and a gate. The fourth transistor includes a current electrode connected to the precharge node, another current electrode connected to the second bit line, and a gate. The control module deactivates the fourth transistor in response to a dummy access of the first storage module at the second transistor.
摘要翻译：一种具有存储节点，预充电节点，第一，第二，第三和第四晶体管以及控制模块的多端口存储器件。第一晶体管包括连接到存储节点的电流电极，连接到第一位线的另一电流电极和连接到第一字线的栅极。第二晶体管包括连接到存储节点的电流电极，连接到第二位线的另一个电流电极和连接到第二字线的栅极。第三晶体管包括连接到参考节点的电流电极，连接到第一位线的另一电流电极和栅极。第四晶体管包括连接到预充电节点的电流电极，连接到第二位线的另一电流电极和栅极。响应于在第二晶体管处的第一存储模块的虚拟访问，控制模块停用第四晶体管。

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