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1. 发明授权

US08766703B1 Method and apparatus for sensing on-chip characteristics 有权
标题翻译：用于感测片上特性的方法和装置
公开(公告)号：US08766703B1
公开(公告)日：2014-07-01
申请号：US13835690
申请日：2013-03-15
申请人： Jianan Yang , James D. Burnett , Mark W. Jetton , Thomas W. Liston
发明人： Jianan Yang , James D. Burnett , Mark W. Jetton , Thomas W. Liston
IPC分类号： H01L35/00 , G05F1/567
CPC分类号： G05F1/567 , G01K7/01 , G01R31/2884 , H01L22/34
摘要： A sensor circuit performs a method for sensing on-chip characteristics. The method includes generating a first voltage using a drive current through a first set of transistors that are operating in saturation mode and generating a second voltage using subthreshold leakage current from a second set of transistors that are in subthreshold mode. The method further includes comparing the second voltage to the first voltage to sense an on-chip characteristic. The sensed on-chip characteristic can be temperature and/or gate length variation.
摘要翻译：传感器电路执行用于检测片上特性的方法。该方法包括利用在饱和模式下工作的第一组晶体管的驱动电流产生第一电压，并使用来自处于亚阈值模式的第二组晶体管的亚阈值泄漏电流产生第二电压。该方法还包括将第二电压与第一电压进行比较以感测片上特性。感测到的片上特性可以是温度和/或栅极长度变化。

2. 发明授权

US09317087B2 Memory column drowsy control 有权
标题翻译：内存列困倦控制
公开(公告)号：US09317087B2
公开(公告)日：2016-04-19
申请号：US13689331
申请日：2012-11-29
申请人： Ravindraraj Ramaraju , Jianan Yang , Mark W. Jetton , Thomas W. Liston , George P. Hoekstra , Andrew C. Russell
发明人： Ravindraraj Ramaraju , Jianan Yang , Mark W. Jetton , Thomas W. Liston , George P. Hoekstra , Andrew C. Russell
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F1/3296 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column.
摘要翻译：根据至少一个实施例，提供列级功率控制粒度以使用昏迷列控制位来控制存储器的低功率状态，以控制单个列级的低功率状态，以保护存储器免于弱位故障。根据至少一个实施例，提供了在存储器阵列中使用专用行位单元的方法，其中行中的每个位控制阵列中相应列的低功率状态。使用特殊的控制信号来访问字线，字线在常规字线地址空间之外。提供了一种机制来指定弱位列，并设置与该特定列相对应的控制位以禁用该列的困倦/低功率状态。

3. 发明授权

US09026808B2 Memory with word level power gating 有权
标题翻译：内存字级电源门控
公开(公告)号：US09026808B2
公开(公告)日：2015-05-05
申请号：US13457248
申请日：2012-04-26
申请人： Jianan Yang , Mark W. Jetton , Thomas W. Liston
发明人： Jianan Yang , Mark W. Jetton , Thomas W. Liston
IPC分类号： G06F1/26 , G06F1/32 , G06F12/00 , G11C8/08 , G11C11/418
CPC分类号： G11C11/418 , G11C8/08
摘要： In accordance with at least one embodiment, memory power gating at word level is provided. In accordance with at least one embodiment, a word level power-gating technique, which is enabled by adding an extra control bit to each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.) of a memory array, provides fine-grained power reduction for a memory array. In accordance with at least one embodiment, a gating transistor is provided for each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.).
摘要翻译：根据至少一个实施例，提供了字级的存储器电源门控。根据至少一个实施例，通过向每个子阵列（例如，每个字，每行，每个字线，每个位线，阵列的每个部分等）添加额外的控制位来实现的字电平门控技术。）存储器阵列，为存储器阵列提供细粒度的功率降低。根据至少一个实施例，为每个子阵列（例如，每个字，每行，每个字线，每个位线，阵列的每个部分等）提供门控晶体管。

4. 发明申请

US20130290750A1 MEMORY WITH WORD LEVEL POWER GATING 有权
标题翻译：记忆与词水平功率增益
公开(公告)号：US20130290750A1
公开(公告)日：2013-10-31
申请号：US13457248
申请日：2012-04-26
申请人： Jianan Yang , Mark W. Jetton , Thomas W. Liston
发明人： Jianan Yang , Mark W. Jetton , Thomas W. Liston
IPC分类号： G06F1/32 , G06F1/00
CPC分类号： G11C11/418 , G11C8/08
摘要： In accordance with at least one embodiment, memory power gating at word level is provided. In accordance with at least one embodiment, a word level power-gating technique, which is enabled by adding an extra control bit to each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.) of a memory array, provides fine-grained power reduction for a memory array. In accordance with at least one embodiment, a gating transistor is provided for each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.).
摘要翻译：根据至少一个实施例，提供了字级的存储器电源门控。根据至少一个实施例，通过向每个子阵列（例如，每个字，每行，每个字线，每个位线，阵列的每个部分等）添加额外的控制位来实现的字电平门控技术。）存储器阵列，为存储器阵列提供细粒度的功率降低。根据至少一个实施例，为每个子阵列（例如，每个字，每行，每个字线，每个位线，阵列的每个部分等）提供门控晶体管。

5. 发明申请

US20130290753A1 MEMORY COLUMN DROWSY CONTROL 有权
标题翻译：记忆柱雨控制
公开(公告)号：US20130290753A1
公开(公告)日：2013-10-31
申请号：US13689331
申请日：2012-11-29
申请人： Ravindraraj Ramaraju , Jianan Yang , Mark W. Jetton , Thomas W. Liston , George P. Hoekstra , Andrew C. Russell
发明人： Ravindraraj Ramaraju , Jianan Yang , Mark W. Jetton , Thomas W. Liston , George P. Hoekstra , Andrew C. Russell
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F1/3296 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column.
摘要翻译：根据至少一个实施例，提供列级功率控制粒度以使用昏迷列控制位来控制存储器的低功率状态，以控制单个列级的低功率状态，以保护存储器免于弱位故障。根据至少一个实施例，提供了在存储器阵列中使用专用行位单元的方法，其中行中的每个位控制阵列中相应列的低功率状态。使用特殊的控制信号来访问字线，字线在常规字线地址空间之外。提供了一种机制来指定弱位列，并设置与该特定列相对应的控制位以禁用该列的困倦/低功率状态。

6. 发明授权

US09123545B2 Semiconductor device with single-event latch-up prevention circuitry 有权
标题翻译：具有单事件闩锁防止电路的半导体器件
公开(公告)号：US09123545B2
公开(公告)日：2015-09-01
申请号：US14188461
申请日：2014-02-24
申请人： Jianan Yang , James D. Burnett , Brad J. Garni , Thomas W. Liston
发明人： Jianan Yang , James D. Burnett , Brad J. Garni , Thomas W. Liston
IPC分类号： H01L29/66 , H01L27/06 , H01L27/092
CPC分类号： H01L27/06 , H01L27/0921
摘要： A semiconductor device includes a parasitic silicon-controlled rectifier (SCR) and a first transistor. The parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The first transistor is coupled between a first power supply node and an emitter of the parasitic pnp BJT. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp BJT following a single-event latch-up (SEL) event.
摘要翻译：半导体器件包括寄生硅可控整流器（SCR）和第一晶体管。寄生SCR包括寄生pnp双极结型晶体管（BJT）和寄生npn BJT。第一晶体管耦合在第一电源节点和寄生pnp BJT的发射极之间。第一晶体管包括耦合到第一电源节点的第一端子，耦合到寄生pnp BJT的发射极的第二端子和控制端子。第一晶体管不位于pnp BJT的基极和第一电源节点之间。在单事件闩锁（SEL）事件之后，第一晶体管限制由寄生pnp BJT传导的电流。

7. 发明授权

US08685800B2 Single event latch-up prevention techniques for a semiconductor device 有权
标题翻译：半导体器件的单事件闭锁预防技术
公开(公告)号：US08685800B2
公开(公告)日：2014-04-01
申请号：US13560010
申请日：2012-07-27
申请人： Jianan Yang , James D. Burnett , Brad J. Garni , Thomas W. Liston , Huy Van Pham
发明人： Jianan Yang , James D. Burnett , Brad J. Garni , Thomas W. Liston , Huy Van Pham
IPC分类号： H01L21/332
CPC分类号： H01L27/06 , H01L27/0921
摘要： A technique for addressing single-event latch-up (SEL) in a semiconductor device includes determining a location of a parasitic silicon-controlled rectifier (SCR) in an integrated circuit design of the semiconductor device. In this case, the parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The technique also includes incorporating a first transistor between a first power supply node and an emitter of the parasitic pnp BJT in the integrated circuit design. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp bipolar junction transistor following an SEL.
摘要翻译：用于在半导体器件中寻址单事件闩锁（SEL）的技术包括在半导体器件的集成电路设计中确定寄生硅控整流器（SCR）的位置。在这种情况下，寄生SCR包括寄生pnp双极结型晶体管（BJT）和寄生npnBJT。该技术还包括在集成电路设计中在第一电源节点和寄生pnp BJT的发射极之间并入第一晶体管。第一晶体管包括耦合到第一电源节点的第一端子，耦合到寄生pnp BJT的发射极的第二端子和控制端子。第一晶体管不位于pnp BJT的基极和第一电源节点之间。第一晶体管限制了在SEL之后由寄生pnp双极结晶体传导的电流。

8. 发明申请

US20140027810A1 SINGLE-EVENT LATCH-UP PREVENTION TECHNIQUES FOR A SEMICONDUCTOR DEVICE 有权
标题翻译：用于半导体器件的单事件闭锁预防技术
公开(公告)号：US20140027810A1
公开(公告)日：2014-01-30
申请号：US13560010
申请日：2012-07-27
申请人： Jianan Yang , James D. Burnett , Brad J. Garni , Thomas W. Liston , Huy Van Pham
发明人： Jianan Yang , James D. Burnett , Brad J. Garni , Thomas W. Liston , Huy Van Pham
IPC分类号： H01L27/06 , G06F17/50
CPC分类号： H01L27/06 , H01L27/0921
摘要： A technique for addressing single-event latch-up (SEL) in a semiconductor device includes determining a location of a parasitic silicon-controlled rectifier (SCR) in an integrated circuit design of the semiconductor device. In this case, the parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The technique also includes incorporating a first transistor between a first power supply node and an emitter of the parasitic pnp BJT in the integrated circuit design. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp bipolar junction transistor following an SEL.
摘要翻译：用于在半导体器件中寻址单事件闩锁（SEL）的技术包括在半导体器件的集成电路设计中确定寄生硅控整流器（SCR）的位置。在这种情况下，寄生SCR包括寄生pnp双极结型晶体管（BJT）和寄生npnBJT。该技术还包括在集成电路设计中在第一电源节点和寄生pnp BJT的发射极之间并入第一晶体管。第一晶体管包括耦合到第一电源节点的第一端子，耦合到寄生pnp BJT的发射极的第二端子和控制端子。第一晶体管不位于pnp BJT的基极和第一电源节点之间。第一晶体管限制了在SEL之后由寄生pnp双极结晶体传导的电流。

9. 发明授权

US08995178B1 SRAM with embedded ROM 有权
标题翻译： SRAM带嵌入式ROM
公开(公告)号：US08995178B1
公开(公告)日：2015-03-31
申请号：US14069192
申请日：2013-10-31
申请人： Jianan Yang , Brad J. Garni , Mark W. Jetton
发明人： Jianan Yang , Brad J. Garni , Mark W. Jetton
IPC分类号： G11C11/00 , G11C11/412 , H01L27/11
CPC分类号： G11C11/412 , G11C14/0054 , G11C17/12 , H01L27/1104
摘要： An integrated circuit includes first and second memory cells including a first pull-up transistor each having a body tie coupled to respective first and second well bias voltages. Drain electrodes of the first and second pull-up transistors are coupled to a first true bit line and a first complementary bit line, respectively. A second memory cell includes first and second pull-up transistors each having a body tie coupled to the second and first well bias voltages, respectively. Drain electrodes of the first and second pull-up transistors are coupled to a second true bit line and a second complementary bit line, respectively. The first well bias voltage is lower than the second well bias voltage during a Read-Only Memory (ROM) mode, and the first well bias voltage is the same as the second well bias voltage during a Static Random Access Memory (SRAM) mode.
摘要翻译：集成电路包括第一和第二存储器单元，其包括第一上拉晶体管，每个第一上拉晶体管具有耦合到相应的第一和第二阱偏置电压的主体带。第一和第二上拉晶体管的漏极分别耦合到第一真位线和第一互补位线。第二存储器单元包括分别具有耦合到第二阱偏置电压和第一阱偏置电压的主体带的第一和第二上拉晶体管。第一和第二上拉晶体管的漏极电极分别耦合到第二真位线和第二互补位线。在只读存储器（ROM）模式期间，第一阱偏置电压低于第二阱偏置电压，并且在静态随机存取存储器（SRAM）模式期间，第一阱偏置电压与第二阱偏置电压相同。

10. 发明授权

US08446176B1 Reconfigurable engineering change order base cell 有权
标题翻译：可重构工程变更订单基本单元格
公开(公告)号：US08446176B1
公开(公告)日：2013-05-21
申请号：US13326556
申请日：2011-12-15
申请人： Jianan Yang , Darrin L. Hutchinson , Stephen G. Jamison
发明人： Jianan Yang , Darrin L. Hutchinson , Stephen G. Jamison
IPC分类号： H01L25/00 , H01L27/088 , H03K19/20 , H03K19/094
CPC分类号： G06F17/5068 , H01L27/0207 , H01L27/092
摘要： An integrated circuit ECO base cell module is formed with PMOS and NMOS gate electrode structures and power supply lines that are electrically separated from one another up to the second metal (M2) layer in a fixed circuit structure that may be reconfigured with one or more conductor elements formed above the M2 layer to form a predetermined circuit function.
摘要翻译：集成电路ECO基电池模块形成有PMOS和NMOS栅极电极结构和电源线，其以固定电路结构彼此电分离直到第二金属（M2）层，其可以用一个或多个导体形成在M2层上方的元件以形成预定的电路功能。

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