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1. 发明授权

US06145043A Boolean and movement accelerator 失效
标题翻译：布尔运动加速器
公开(公告)号：US06145043A
公开(公告)日：2000-11-07
申请号：US92101
申请日：1998-06-05
申请人： Terence Sych , Byron R. Gillespie , Ravi S. Rao
发明人： Terence Sych , Byron R. Gillespie , Ravi S. Rao
IPC分类号： G06F9/308 , G06F9/38 , G06F11/10 , G06F13/00 , G06F7/00 , H03K19/00
CPC分类号： G06F9/30018 , G06F11/1076 , G06F9/3816 , G06F9/3879
摘要： An application accelerator (AA) unit that in one embodiment is part of an I/O processor (IOP) integrated circuit. The AAU includes logic circuitry for improving the performance of storage applications such as Redundant Array of Inexpensive Disks (RAID). A boolean unit performs operations such as exclusive-or (XOR) on multiple blocks of data to form the image parity block which is written to the redundant disk array. The AAU is associated with a memory-mapped programming interface that allows software executed by a core processor in the IOP to utilize the AAU for accelerating RAID storage applications as well as local memory DMA-type transfers, using the descriptor construct.
摘要翻译：一种应用加速器（AA）单元，其在一个实施例中是I / O处理器（IOP）集成电路的一部分。 AAU包括用于提高存储应用的性能的逻辑电路，例如廉价磁盘冗余阵列（RAID）。布尔单元在多个数据块上执行诸如异或（XOR）的操作，以形成写入冗余磁盘阵列的图像奇偶校验块。 AAU与内存映射编程接口相关联，允许由IOP中的核心处理器执行的软件利用AAU来加速RAID存储应用以及使用描述符构造的本地存储器DMA类型传输。

2. 发明授权

US06460107B1 Integrated real-time performance monitoring facility 失效
标题翻译：集成实时性能监控设备
公开(公告)号：US06460107B1
公开(公告)日：2002-10-01
申请号：US09301870
申请日：1999-04-29
申请人： Ravi S. Rao , Byron R. Gillespie , Elliot Garbus , Dinesh Ranganathan
发明人： Ravi S. Rao , Byron R. Gillespie , Elliot Garbus , Dinesh Ranganathan
IPC分类号： G06F1314
CPC分类号： G06F11/3409 , G06F11/348 , G06F11/349 , G06F2201/86 , G06F2201/87 , G06F2201/88
摘要： Real-time performance monitoring facility in an integrated circuit (IC) data processor for monitoring events related to different bus activity. The monitoring facility is accessible via a bus connection the IC. Events include device acquisition and ownership time, and the number of requests and grants on a given bus. The events are counted as occurrences and durations by a number of event counters integrated in the IC. The IC can notify software when the counters overflow. The IC may feature multiple clock domains, including, for instance, multiple bus interfaces operating at different clock frequencies, in which events from different clock domains may be tracked by the same counter. In one embodiment, the performance monitoring facility is integrated into an I/O processor (IOP) die that complies with the popular intelligent I/O (I2O) and Peripheral Components Interconnect (PCI) specifications.
摘要翻译：集成电路（IC）数据处理器中的实时性能监控设备，用于监控与不同总线活动相关的事件。监控设备可通过总线连接IC访问。事件包括设备采集和所有权时间，以及给定总线上的请求和授权数量。这些事件由集成在IC中的多个事件计数器计入事件和持续时间。当计数器溢出时，IC可以通知软件。 IC可以具有多个时钟域，包括例如以不同时钟频率工作的多个总线接口，其中来自不同时钟域的事件可以被同一计数器跟踪。在一个实施例中，性能监视设备被集成到符合流行的智能I / O（I2O）和外围组件互连（PCI）规范的I / O处理器（IOP）芯片中。

3. 发明授权

US06678777B2 Integrated real-time performance monitoring facility 失效
标题翻译：集成实时性能监控设备
公开(公告)号：US06678777B2
公开(公告)日：2004-01-13
申请号：US10254408
申请日：2002-09-25
申请人： Ravi S. Rao , Byron R. Gillespie , Elliot Garbus
发明人： Ravi S. Rao , Byron R. Gillespie , Elliot Garbus
IPC分类号： G06F1314
CPC分类号： G06F11/3409 , G06F11/348 , G06F11/349 , G06F2201/86 , G06F2201/87 , G06F2201/88
摘要： Real-time performance monitoring facility in an integrated circuit (IC) data processor for monitoring events related to different bus activity. The monitoring facility is accessible via a bus connection the IC. Events include device acquisition and ownership time, and the number of requests and grants on a given bus. The events are counted as occurrences and durations by a number of event counters integrated in the IC. The IC can notify software when the counters overflow. The IC may feature multiple clock domains, including, for instance, multiple bus interfaces operating at different clock frequencies, in which events from different clock domains may be tracked by the same counter. In one embodiment, the performance monitoring facility is integrated into an I/O processor (IOP) die that complies with the popular intelligent I/O (I2O) and Peripheral Components Interconnect (PCI) specifications.
摘要翻译：集成电路（IC）数据处理器中的实时性能监控设备，用于监控与不同总线活动相关的事件。监控设备可通过总线连接IC访问。事件包括设备采集和所有权时间，以及给定总线上的请求和授权数量。这些事件由集成在IC中的多个事件计数器计入事件和持续时间。当计数器溢出时，IC可以通知软件。 IC可以具有多个时钟域，包括例如以不同时钟频率工作的多个总线接口，其中来自不同时钟域的事件可以被同一计数器跟踪。在一个实施例中，性能监视设备被集成到符合流行的智能I / O（I2O）和外围组件互连（PCI）规范的I / O处理器（IOP）芯片中。

4. 发明授权

US6088421A Method and apparatus for providing scaled ratio counters to obtain agent profiles 失效
标题翻译：用于提供比例计数器以获得代理简档的方法和装置
公开(公告)号：US6088421A
公开(公告)日：2000-07-11
申请号：US123855
申请日：1998-07-28
申请人： Ravi S. Rao , Elliot D. Garbus
发明人： Ravi S. Rao , Elliot D. Garbus
IPC分类号： G06F7/62 , G06F11/34 , H03K21/00
CPC分类号： G06F7/62 , G06F11/348 , G06F2201/86 , G06F2201/88
摘要： A method and apparatus for monitoring an event is disclosed. In one embodiment, a ratio counter is provided which includes a first counter having a first count and a second counter having a second count. The method increments the first count of the first counter on an occurrence of an event by a first device and shifts the ratio counter to the right by a predetermined number of bits when the first count reaches a maximum count. The method further takes a ratio between the first count and the second count where the ratio indicates the relative occurrence of the event by the first device and a second device. In another embodiment, the method decrements the second count of the second counter when the first count reaches a maximum count. In yet another embodiment, the method decrements the first count of the first counter and the second count of the second counter when the first count reaches a maximum count.
摘要翻译：公开了一种用于监视事件的方法和装置。在一个实施例中，提供一种比率计数器，其包括具有第一计数的第一计数器和具有第二计数的第二计数器。该方法在第一设备发生事件时增加第一计数器的第一计数，并且当第一计数达到最大计数时，将比例计数器向右移位预定比特数。该方法还采用第一计数和第二计数之间的比率，其中该比率指示由第一设备和第二设备发生事件的相对发生。在另一实施例中，当第一计数达到最大计数时，该方法递减第二计数器的第二计数。在另一个实施例中，当第一计数达到最大计数时，该方法递减第一计数器的第一计数和第二计数器的第二计数。

5. 发明授权

US06070182A Data processor having integrated boolean and adder logic for accelerating storage and networking applications 失效
标题翻译：具有集成布尔和加法器逻辑的数据处理器，用于加速存储和联网应用
公开(公告)号：US06070182A
公开(公告)日：2000-05-30
申请号：US92275
申请日：1998-06-05
申请人： Ravi S. Rao , Byron R. Gillespie , Elliot Garbus , Joseph Murray
发明人： Ravi S. Rao , Byron R. Gillespie , Elliot Garbus , Joseph Murray
IPC分类号： G06F7/57 , G06F11/10 , G06F7/50
CPC分类号： G06F7/57 , G06F11/1076
摘要： An application accelerator unit (AAU) that is integrated as part of a data processor, such as an I/O processor (IOP) integrated circuit. In one embodiment, the AAU includes logic for improving the performance of storage applications such as Redundant Array of Inexpensive Disks (RAID). The AAU performs boolean operations such as exclusive-or (XOR) on multiple blocks of data to form the image parity block which is then written to the redundant disk array. Additionally, the AAU may feature adder logic configured to perform an addition such as a network header checksum calculation on each data packet. The AAU includes a memory-mapped programming interface that allows software executed by a core processor in the IOP to utilize the AAU for accelerating storage and networking applications as well as for local memory DMA-type transfers, using the chain descriptor construct.
摘要翻译：作为诸如I / O处理器（IOP）集成电路的数据处理器的一部分集成的应用加速器单元（AAU）。在一个实施例中，AAU包括用于改善诸如廉价磁盘冗余阵列（RAID）的存储应用的性能的逻辑。 AAU在多个数据块上执行布尔运算（例如异或（XOR））以形成图像奇偶校验块，然后将其写入冗余磁盘阵列。此外，AAU可以具有加法器逻辑，其被配置为对每个数据分组执行诸如网络报头校验和计算的相加。 AAU包括内存映射编程接口，允许IOP中的核心处理器执行的软件利用AAU来加速存储和联网应用以及使用链描述符构造的本地存储器DMA类型传输。

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