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1. 发明授权

US11610987B2 NPNP layered MOS-gated trench device having lowered operating voltage 有权
公开(公告)号：US11610987B2
公开(公告)日：2023-03-21
申请号：US17539063
申请日：2021-11-30
申请人： Pakal Technologies, LLC
发明人： Paul M Moore , Vladimir Rodov , Richard A Blanchard
IPC分类号： H01L29/745 , H01L29/423
摘要： An npnp layered switch is modified to have a composite anode structure. Instead of the continuous p-type bottom anode layer of a typical npnp IGTO device, thyristor, or IGBT, the composite anode is formed of a segmented p-type layer with gaps containing n-type semiconductor material. The n-type material forms a majority carrier path between the bottom anode electrode and the n-type collector of the vertical npn bipolar transistor. When a trenched gate is biased high, the majority carrier path is created between the bottom anode electrode and the top cathode electrode. Such a current path operates at very low operating voltages, starting at slightly above 0 volts. Above operating voltages of about 1.0 volts, the npnp layered switch operates normally and uses regenerative bipolar transistor action to conduct a vast majority of the current. The two current paths conduct in parallel.

2. 发明授权

US10256331B2 Insulated gate turn-off device having low capacitance and low saturation current 有权
公开(公告)号：US10256331B2
公开(公告)日：2019-04-09
申请号：US15910482
申请日：2018-03-02
申请人： Pakal Technologies, LLC
发明人： Hidenori Akiyama , Richard A. Blanchard , Woytek Tworzydlo , Vladimir Rodov
IPC分类号： H01L29/732 , H01L29/745 , H01L29/06 , H01L29/66 , H01L29/739
摘要： An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a P+ layer (e.g., a substrate), an N− epi layer, a P-well, vertical insulated gates formed in the P-well, and N+ regions between at least some of the gates, so that vertical NPN and PNP transistors are formed. A source/emitter electrode is on top, and a drain/cathode electrode is on the bottom of the substrate. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gates, referenced to the source/emitter electrode. Some of the cells are passive, having gates that are either not connected to the active gates or having gates that are shorted to their associated N+ regions, to customize the input capacitance and lower the saturation current. Other techniques are described to form the passive cells.

3. 发明申请

US20180254336A1 INSULATED GATE TURN-OFF DEVICE HAVING LOW CAPACITANCE AND LOW SATURATION CURRENT 审中-公开
公开(公告)号：US20180254336A1
公开(公告)日：2018-09-06
申请号：US15910482
申请日：2018-03-02
申请人： Pakal Technologies, LLC
发明人： Hidenori Akiyama , Richard A. Blanchard , Woytek Tworzydlo , Vladimir Rodov
IPC分类号： H01L29/745 , H01L29/06
CPC分类号： H01L29/7455 , H01L29/0623 , H01L29/0696 , H01L29/66303 , H01L29/66363 , H01L29/7397
摘要： An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a P+ layer (e.g., a substrate), an N− epi layer, a P-well, vertical insulated gates formed in the P-well, and N+ regions between at least some of the gates, so that vertical NPN and PNP transistors are formed. A source/emitter electrode is on top, and a drain/cathode electrode is on the bottom of the substrate. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gates, referenced to the source/emitter electrode. Some of the cells are passive, having gates that are either not connected to the active gates or having gates that are shorted to their associated N+ regions, to customize the input capacitance and lower the saturation current. Other techniques are described to form the passive cells.

4. 发明申请

US20140034995A1 ACTIVE EDGE STRUCTURES PROVIDING UNIFORM CURRENT FLOW IN INSULATED GATE TURN-OFF THYRISTORS 有权
标题翻译：主动边缘结构提供绝缘闸门平衡电流平均流量
公开(公告)号：US20140034995A1
公开(公告)日：2014-02-06
申请号：US13953366
申请日：2013-07-29
申请人： Pakal Technologies LLC
发明人： Hidenori Akiyama , Richard A. Blanchard , Woytek Tworzydlo
IPC分类号： H01L29/745
CPC分类号： H01L29/7455 , H01L29/0619
摘要： An insulated gate turn-off thyristor, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n− layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The thyristor is formed of a matrix of cells. Due to the discontinuity along the edge cells, a relatively large number of holes are injected into the n− epi layer and drift into the edge p-well, normally creating a higher current along the edge and lowering the breakover voltage of the thyristor. To counter this effect, the dopant concentration of the n+ region(s) near the edge is reduced to reduce the NPN transistor beta and current along the edge, thus increasing the breakover voltage. Alternatively, a deep trench may circumscribe the edge cells to provide isolation from the injected holes.
摘要翻译：形成为管芯的绝缘栅极截止晶闸管具有包括形成在p阱中的p +层（例如，衬底），n层，p阱，垂直绝缘栅极区域的分层结构，以及 n +区域，从而形成垂直NPN和PNP晶体管。晶闸管由电池基体形成。由于沿着边缘单元的不连续性，相当多的孔注入到n-epi层中并漂移到边缘p阱中，通常沿着边缘产生更高的电流并降低晶闸管的断开电压。为了抵消这种影响，边缘附近的n +区域的掺杂剂浓度降低，以减小沿着边缘的NPN晶体管β和电流，从而增加了突变电压。或者，深沟槽可以围绕边缘细胞以提供与注入的孔的隔离。

5. 发明授权

US09935188B2 Insulated gate turn-off device with turn-off Schottky-Barrier MOSFET 有权
公开(公告)号：US09935188B2
公开(公告)日：2018-04-03
申请号：US15655715
申请日：2017-07-20
申请人： Pakal Technologies, LLC
发明人： Richard A. Blanchard , Vladimir Rodov , Hidenori Akiyama , Woytek Tworzydlo
IPC分类号： H01L29/78 , H01L29/739 , H01L29/47 , H01L29/10 , H01L29/08 , H01L27/07
CPC分类号： H01L29/7396 , H01L27/0716 , H01L29/083 , H01L29/0839 , H01L29/105 , H01L29/456 , H01L29/47 , H01L29/7455 , H01L29/7813 , H01L29/7839
摘要： An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n− epi layer, a p-well, vertical insulated gate electrodes formed in the p-well, and n+ regions between the gate electrodes, so that vertical npn and pnp transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate electrodes, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for shorting the base of the npn transistor to its emitter, to turn the npn transistor off when the p-channel MOSFET is turned on by a slight negative voltage applied to the gate. The p-channel MOSFET includes a Schottky source formed in the top surface of the npn transistor emitter.

6. 发明授权

US09806152B2 Vertical insulated gate turn-off thyristor with intermediate p+ layer in p-base 有权
公开(公告)号：US09806152B2
公开(公告)日：2017-10-31
申请号：US15448530
申请日：2017-03-02
申请人： Pakal Technologies, LLC
发明人： Hidenori Akiyama
IPC分类号： H01L29/00 , H01L29/10 , H01L29/745 , H01L29/423 , H01L29/74 , H01L29/744 , H01L29/66 , H01L29/78
CPC分类号： H01L29/102 , H01L29/0696 , H01L29/0839 , H01L29/41716 , H01L29/4236 , H01L29/66734 , H01L29/744 , H01L29/745 , H01L29/7455 , H01L29/7827 , H01L2924/1301 , H01L2924/1302 , H01L2924/13021 , H01L2924/13022
摘要： An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n-epi layer, a p-well, vertical insulated gate regions formed in the p-well, and an n-layer over the p-well and between the gate regions, so that vertical npn and pnp transistors are formed. The p-well has an intermediate highly doped portion. When the gate regions are sufficiently biased, an inversion layer surrounds the gate regions, causing the effective base of the npn transistor to be narrowed to increase its beta. When the product of the betas exceeds one, controlled latch-up of the thyristor is initiated. The p-well's highly doped intermediate region enables improvement in the npn transistor efficiency as well as enabling more independent control over the characteristics of the n-type layer (emitter), the emitter-base junction characteristics, and the overall dopant concentration and thickness of the p-type base.

7. 发明申请

US20150349104A1 INSULATED GATE TURN-OFF DEVICE WITH TURN-OFF TRANSISTOR 有权
标题翻译：具有关断晶体管的绝缘栅开关装置
公开(公告)号：US20150349104A1
公开(公告)日：2015-12-03
申请号：US14701168
申请日：2015-04-30
申请人： Pakal Technologies, LLC
发明人： Vladimir Rodov , Hidenori Akiyama , Richard A. Blanchard , Woytek Tworzydlo
IPC分类号： H01L29/745 , H01L29/423 , H01L29/06
CPC分类号： H01L29/7455 , H01L29/0619 , H01L29/0696 , H01L29/0839 , H01L29/4236
摘要： An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n− epi layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for shorting the base of the NPN transistor to its emitter, to turn the NPN transistor off when the p-channel MOSFET is turned on by a slight negative voltage applied to the gate. This allows the IGTO device to be more easily turned off while in a latch-up condition, when the device is acting like a thyristor.
摘要翻译：形成为管芯的绝缘栅极关闭（IGTO）器件具有包括p +层（例如，衬底），n-外延层，p阱，形成在p中的垂直绝缘栅极区域的分层结构并且在栅极区之间加上n +区，从而形成垂直的NPN和PNP晶体管。该装置由一个单元矩阵组成。为了打开器件，正极施加正电压，参考阴极。电池还包含垂直的p沟道MOSFET，用于将NPN晶体管的基极短路到其发射极，以在p沟道MOSFET通过施加到栅极的轻微的负电压导通时关断NPN晶体管。这允许当器件像闸流管一样工作时，IGTAG器件在闩锁状态下更容易关闭。

8. 发明授权

US08937502B2 Lateral insulated gate turn-off devices 有权
标题翻译：横向绝缘门关闭装置
公开(公告)号：US08937502B2
公开(公告)日：2015-01-20
申请号：US14191937
申请日：2014-02-27
申请人： Pakal Technologies, LLC
发明人： Richard A. Blanchard , Hidenori Akiyama , Woytek Tworzydlo
IPC分类号： H03K17/04 , H01L29/745 , H01L29/739
CPC分类号： H01L29/7455 , H01L29/0696 , H01L29/7393 , H01L29/7395 , H01L29/7436 , H03K17/0403
摘要： A lateral insulated gate turn-off (IGTO) device includes an n-type layer, a p-well formed in the n-type layer, a shallow n+ type region formed in the well, a shallow p+ type region formed in the well, a cathode electrode shorting the n+ type region to the p+ type region, at least one trenched gate extending through the n+ type region and into the well, a p+ type anode region laterally spaced from the well, and an anode electrode electrically contacting the p+ type anode region. The structure forms a lateral structure of NPN and PNP transistors, where the well forms the base of the NPN transistor. When a turn-on voltage is applied to the gate, the p-base has a reduced width, resulting in the beta of the NPN transistor increasing beyond a threshold to turn on the IGTO device by current feedback.
摘要翻译：横向绝缘栅极截止（IGTO）器件包括n型层，形成在n型层中的p阱，形成在阱中的浅n +型区，形成在阱中的浅p +型区，将n +型区域短路到p +型区域的阴极电极，延伸穿过n +型区域并进入阱的至少一个沟槽栅极，与阱横向间隔开的p +型阳极区域和与p +型电极接触的阳极电极阳极区域。该结构形成NPN和PNP晶体管的横向结构，其中阱形成NPN晶体管的基极。当导通电压施加到栅极时，p基极具有减小的宽度，导致NPN晶体管的β增加超过阈值，以通过电流反馈来接通IGTO器件。

9. 发明授权

US08803191B2 Systems, devices, and methods with integrable FET-controlled lateral thyristors 有权
标题翻译：具有可集成FET控制横向晶闸管的系统，器件和方法
公开(公告)号：US08803191B2
公开(公告)日：2014-08-12
申请号：US13652335
申请日：2012-10-15
申请人： Pakal Technologies, LLC
发明人： Richard A. Blanchard
IPC分类号： H01L29/74
CPC分类号： H01L29/7436 , H01L29/66393 , H01L29/7455 , H01L29/8611
摘要： Methods and systems for lateral switched-emitter thyristors in a single-layer implementation. Lateral operation is advantageously achieved by using an embedded gate. Embedded gate plugs are used to controllably invert a portion of the P-base region, so that the electron population at the portion of the inversion layer which is closest to the anode will provide a virtual emitter, and will provide sufficient gain so that the combination of bipolar devices will go into latchup.
摘要翻译：在单层实现中横向开关 - 发射极晶闸管的方法和系统。有利地通过使用嵌入式门来实现横向操作。嵌入式栅极插头用于可控制地反转一部分P基极区域，使得最靠近阳极的反型层部分处的电子群体将提供虚拟发射极，并且将提供足够的增益，使得组合的双极器件将进入闭锁。

10. 发明授权

US08742456B2 Integrating a trench-gated thyristor with a trench-gated rectifier 有权
标题翻译：将沟槽门控晶闸管与沟槽门控整流器集成
公开(公告)号：US08742456B2
公开(公告)日：2014-06-03
申请号：US14059888
申请日：2013-10-22
申请人： Pakal Technologies, LLC
发明人： Hidenori Akiyama , Richard A. Blanchard , Woytek Tworzydlo
IPC分类号： H01L29/02
CPC分类号： H01L29/7416 , H01L21/20 , H01L29/0619 , H01L29/0638 , H01L29/0834 , H01L29/407 , H01L29/42308 , H01L29/66378 , H01L29/742 , H01L29/7455 , H01L29/861
摘要： An integrated trench-MOS-controlled-thyristor plus trench gated diode combination, in which the trenches are preferably formed at the same time. A backside polarity reversal process permits a backside p+ region in the thyristor areas, and only a backside n+ region in the diode areas (for an n-type device). This is particularly advantageous in motor control circuits and the like, where the antiparallel diode permits the thyristor to be dropped into existing power MOSFET circuit designs. In power conversion circuits, the antiparallel diode can conveniently serve as a freewheeling diode.
摘要翻译：集成沟槽MOS控制晶闸管和沟槽门控二极管组合，其中沟槽优选同时形成。背面极性反转处理允许晶闸管区域中的背面p +区域，并且仅在二极管区域（用于n型器件）中的背面n +区域。这在电动机控制电路等中是特别有利的，其中反并联二极管允许晶闸管掉入现有的功率MOSFET电路设计中。在功率转换电路中，反并联二极管可以方便地用作续流二极管。

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