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    • 1. 发明授权
    • Dynamic ram having multiplexed twin I/O line pairs
    • 具有复用双I / O线对的动态RAM
    • US4754433A
    • 1988-06-28
    • US908440
    • 1986-09-16
    • Daeje ChinWei HwangNicky C. Lu
    • Daeje ChinWei HwangNicky C. Lu
    • G11C11/401G11C7/10G11C11/409G11C11/4096G11C7/00
    • G11C11/4096G11C7/1021G11C7/1033G11C7/1048
    • A dynamic random access memory (DRAM) is comprised of a first and a second input/output (I/O) bus, a first and a second I/O sense amplifier, and a first and a second I/O bus precharge circuit. A control circuit is responsive to the state of a mode control signal for enabling the operation of the I/O buses and the precharge circuits such that in one mode of operation the DRAM operates in a conventional single bit per CAS cycle page mode. In a second mode of operation a high speed dual bit per CAS cycle page mode is achieved, wherein the I/O buses are alternately enabled, one being enabled when CAS is asserted and the other being enabled when CAS is deasserted. The dual bit mode of operation provides also for precharging the I/O bus which is not enabled during the period when the other bus is enabled. Thus, in the dual bit mode of operation data transfers to or from the DRAM occur both when CAS is asserted and also when CAS is deasserted, thereby doubling the data transfer rate over that of the conventional page mode of operation.
    • 动态随机存取存储器(DRAM)由第一和第二输入/输出(I / O)总线,第一和第二I / O读出放大器以及第一和第二I / O总线预充电电路组成。 控制电路响应于模式控制信号的状态,以使得I / O总线和预充电电路的操作能够使得在一种操作模式下,DRAM以每个CAS循环页面模式以常规单位操作。 在第二种操作模式下,实现了每个CAS循环页面模式的高速双位模式,其中I / O总线被交替使能,一个在CAS被断言时被使能,另一个在CAS被取消置位时使能。 双位操作模式还用于对在其他总线使能的时段内未使能的I / O总线进行预充电。 因此,在双位操作模式下,当CAS被断言并且当CAS被断言时,数据传送到DRAM或从DRAM发生的数据传输速率超过常规页面操作模式的数据传输速率。
    • 2. 发明授权
    • Boost word-line clock and decoder-driver circuits in semiconductor
memories
    • 升压半导体存储器中的字线时钟和解码器驱动电路
    • US4678941A
    • 1987-07-07
    • US727301
    • 1985-04-25
    • Hu H. ChaoNicky C. Lu
    • Hu H. ChaoNicky C. Lu
    • G11C11/407G11C8/08G11C8/10G11C8/18H03K19/096
    • G11C8/08G11C8/10G11C8/18
    • A CMOS boost word-line clock and decoder-driver circuit which can be used for CMOS DRAM's with substrate bias in addition to VDD supply. A boost word-line clock circuit including simple CMOS inverters is used for the word-line boost and the possible voltage overshoot, which usually occurs because of capacitor two-way boost, can be completely eliminated. Also, the circuit can be triggered by a single clock. A high performance decoder circuit is provided in combination with the aforesaid CMOS boost word-line clock circuit, such decoder using NMOS pass-gate in the decoder driver and providing fast word-line boosting. The timing between the decoder and the word-line clock activation is not crucial.
    • 一个CMOS升压字线时钟和解码器驱动电路,可以用于具有衬底偏置的CMOS DRAM以及VDD电源。 包括简单CMOS反相器的升压字线时钟电路用于字线升压,并且由于电容器双向升压而通常发生的可能的电压过冲可以被完全消除。 此外,电路可以由单个时钟触发。 与上述CMOS升压字线时钟电路组合提供了一种高性能解码器电路,这种解码器在解码器驱动器中使用NMOS通道并提供快速的字线升压。 解码器和字线时钟激活之间的时序并不重要。
    • 7. 发明授权
    • Wordline voltage boosting circuits for complementary MOSFET dynamic
memories
    • 用于互补MOSFET动态存储器的字线升压电路
    • US4954731A
    • 1990-09-04
    • US344340
    • 1989-04-26
    • Sang H. DhongWei HwangNicky C. Lu
    • Sang H. DhongWei HwangNicky C. Lu
    • G11C11/407G11C11/408H03K5/02
    • G11C11/4085H03K5/023
    • Two embodiments of a wordline boost clock circuit that can be used in high speed DRAM circuits are disclosed. The clock circuits require only one boost capacitor and discharge the wordlines faster, improving the DRAM access time. The basic feature of the clock circuit is in the floating gate structure of the nmos device which drives the load to negative during the boosting. In the first embodiment of the clock, the gate of a first device is connected to a first node through a second device. A second node, connected to a wordline, is discharged through the first and a third device when a third node is high with a fourth node low. After a sufficient discharge of the second node, the fourth node is pulled to VDD turning the second device on and a fourth device off. The first (NMOS) transistor has its gate and drain connected together and forms a diode. When a boost capacitor pulls the first node down to negative, the first device stays completely off because of its diode configuration and the second node is pulled to negative through the third device. In the second embodiment, a first device is connected between a boost capacitor and a second node. The load is discharged through a third device with a fourth device on but a first and second device off. After a sufficient discharge of the load, a fourth device is turned off but a second device is turned on, making the third device a diode. When a fifth node is pulled to ground, the second node is pulled down to negative with the first device on. In the second embodiment circuit, the load discharges through only one nmos device and consequently discharges faster than the circuit of the first embodiment.
    • 9. 发明授权
    • Dynamic ram cell with MOS trench capacitor in CMOS
    • 具有MOS沟槽电容器的动态RAM单元
    • US4688063A
    • 1987-08-18
    • US920916
    • 1986-10-21
    • Nicky C. LuTak H. NingLewis M. Terman
    • Nicky C. LuTak H. NingLewis M. Terman
    • H01L27/108H01L29/94H01L29/78
    • H01L27/10832H01L29/945
    • This invention relates generally to Dynamic Random Access Memory (DRAM) cells and more particularly relates to a DRAM cell wherein the storage capacitor of the cell is disposed in a trench formed in a semiconductor substrate. Still more particularly, it relates to a DRAM cell wherein at least a portion of the substrate is heavily doped and forms the counterelectrode of the storage capacitor while a heavily doped polycrystalline plug disposed in the trench capacitor forms the other electrode of the storage capacitor. The DRAM cell includes a field effect access transistor disposed in a well which is opposite in conductivity type to that of the substrate. The well itself is formed in a lightly doped portion of the substrate and may be n or p-type conductivity with the other portions of the cell having conductivity types appropriate for devices fabricated in the CMOS environment. The trench capacitor extends from the surface of the well through the well and lightly doped substrate portion into the heavily doped portion of the substrate. The electrode disposed in the trench is directly connected to the source/drain of the access transistor.
    • 本发明一般涉及动态随机存取存储器(DRAM)单元,更具体地说,涉及一种DRAM单元,其中单元的存储电容器设置在形成于半导体衬底中的沟槽中。 更具体地说,本发明涉及一种DRAM单元,其中基板的至少一部分被重掺杂并形成存储电容器的反电极,而设置在沟槽电容器中的重掺杂多晶硅形成存储电容器的另一个电极。 DRAM单元包括放置在与衬底的导电类型相反的阱中的场效应存取晶体管。 阱本身形成在衬底的轻掺杂部分中,并且可以是n型或p型导电性,其中电池的其它部分具有适合于在CMOS环境中制造的器件的导电类型。 沟槽电容器从阱的表面延伸穿过阱和轻掺杂衬底部分到衬底的重掺杂部分。 设置在沟槽中的电极直接连接到存取晶体管的源极/漏极。
    • 10. 发明授权
    • Trench-capacitor-one-transistor storage cell and array for dynamic
random access memories
    • 用于动态随机存取存储器的沟槽电容器一晶体管存储单元和阵列
    • US5198995A
    • 1993-03-30
    • US605892
    • 1990-10-30
    • Robert H. DennardNicky C. Lu
    • Robert H. DennardNicky C. Lu
    • G11C11/4091H01L27/108
    • G11C11/4091H01L27/10829
    • Lightly Depleted PMOS (LDP) substrate-plate trench-capacitor (SPT) cell Array architecture is disclosed including three types of devices: An enhancement NMOS transistor (ENMOS) which has a n+ poly gate with a positive threshold voltage range, an enhancement PMOS transistor (EPMOS) having a p+ poly gate with a negative threshold voltage range, and a lightly depleted PMOS transistor (LDPMOS) having a p+ poly gate. The LDPMOS is used as the access transistor in the SPT cell with body biased at the power supply voltage VDD, and can also be used in the write drivers. A sense amplifier is included which is a CMOS cross-coupled latch. An n-well is biased at a lower voltage than VDD, such as (VDD--Vg) where Vg is the silicon bandgap, and the lower thresholds enhance faster sensing. The CMOS cross-coupled latch is activated by turning on latching devices. The bitlines are prevented from charging to greater than VDD--Vg, which could cause the array devices of unselected cells to conduct current and alter the stored low-voltage state of such cells.
    • 公开了具有三种类型器件的轻度耗尽的PMOS(LDP)衬底板沟槽电容器(SPT)单元阵列结构:具有正阈值电压范围的n +多晶硅栅极的增强型NMOS晶体管(ENMOS),增强型PMOS晶体管 (EPMOS)具有负阈值电压范围的p +多晶硅栅极,以及具有p +多晶硅栅极的低耗尽PMOS晶体管(LDPMOS)。 LDPMOS用作SPT单元中的存取晶体管,其主体在电源电压VDD处偏置,并且也可用于写入驱动器。 包括一个CMOS交叉耦合锁存器的读出放大器。 n阱被偏置在比VDD低的电压,例如(VDD-Vg),其中Vg是硅带隙,并且下阈值增强更快的感测。 通过开启锁存器件来激活CMOS交叉耦合锁存器。 阻止位线大于VDD-Vg,这可能导致未选择的单元的阵列器件导通电流并改变这种单元的存储的低电压状态。