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1. 发明授权

US08592893B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08592893B2
公开(公告)日：2013-11-26
申请号：US13052893
申请日：2011-03-21
申请人： Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Shunji Taniuchi , Miho Watanabe
发明人： Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Shunji Taniuchi , Miho Watanabe
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/408 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/66734 , H01L29/7811
摘要： According to one embodiment, a power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type, a fourth semiconductor layer, a fifth semiconductor layer, a first and second main electrode, a first and second insulating film and a control electrode. The second and third layers are provided periodically on the first layer. The fourth layer is provided on the third layer. The fifth layer is selectively provided on the fourth layer. The first film is provided on sidewalls of a trench that reaches from a surface of the fifth layer to the second layer. The second film is provided closer to a bottom side of the trench than the first film and has a higher permittivity than the first film. The control electrode is embedded in the trench.
摘要翻译：根据一个实施例，功率半导体器件包括第一导电类型的第一半导体层，第一导电类型的第二半导体层和第二导电类型的第三半导体层，第四半导体层，第五半导体层，第一和第二主电极，第一和第二绝缘膜和控制电极。第二层和第三层周期性地设置在第一层上。第四层设置在第三层上。第五层选择性地设置在第四层上。第一膜设置在从第五层的表面到第二层的沟槽的侧壁上。第二膜比第一膜更靠近沟槽的底侧，并且具有比第一膜更高的介电常数。控制电极嵌入沟槽中。

2. 发明申请

US20100308399A1 POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件
公开(公告)号：US20100308399A1
公开(公告)日：2010-12-09
申请号：US12728823
申请日：2010-03-22
申请人： Wataru SAITO , Syotaro ONO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
发明人： Wataru SAITO , Syotaro ONO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0619 , H01L29/0626 , H01L29/0634 , H01L29/0657 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/7808 , H01L29/7811 , H01L29/7828
摘要： A power semiconductor device includes: a first semiconductor layer of the first conduction type; second semiconductor layers of the first conduction type and third semiconductor layers of the second conduction type alternately provided transversely on the first semiconductor layer; fourth semiconductor layers of the second conduction type provided on the surfaces of the third semiconductor layers; fifth semiconductor layers of the first conduction type provided selectively on the surfaces of the fourth semiconductor layer; sixth semiconductor layers of the second conduction type and seventh semiconductor layers of the first conduction type alternately provided transversely on the second and the third semiconductor layers; a first main electrode electrically connected to the first semiconductor layer; an insulation film provided on the fourth semiconductor layers, the sixth semiconductor layers and the seventh semiconductor layers; a control electrode provided on the fourth semiconductor layers, the sixth semiconductor layers and the seventh semiconductor layers via the insulation film; and a second main electrode joined to the surfaces of the fourth semiconductor layers and the fifth semiconductor layers, the sixth semiconductor layers being connected to the fourth semiconductor layers and to at least one of the third semiconductor layers, which is provided between two of the fourth semiconductor layers, and an impurity concentration of the third semiconductor layers provided below the sixth semiconductor layers being higher than an impurity concentration of the third semiconductor layers provided under the fourth semiconductor layers.
摘要翻译：功率半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层和第二导电类型的第三半导体层交替地设置在第一半导体层上; 设置在第三半导体层的表面上的第二导电类型的第四半导体层; 选择性地在第四半导体层的表面上提供第一导电类型的第五半导体层; 第二导电类型的第六半导体层和第一导电类型的第七半导体层交替地设置在第二和第三半导体层上; 电连接到第一半导体层的第一主电极; 设置在第四半导体层，第六半导体层和第七半导体层上的绝缘膜; 设置在第四半导体层上的控制电极，第六半导体层和第七半导体层经由绝缘膜; 以及与所述第四半导体层和所述第五半导体层的表面接合的第二主电极，所述第六半导体层与所述第四半导体层连接，并且至少一个所述第三半导体层设置在所述第四半导体层并且设置在第六半导体层下方的第三半导体层的杂质浓度高于设置在第四半导体层下方的第三半导体层的杂质浓度。

3. 发明申请

US20100264489A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100264489A1
公开(公告)日：2010-10-21
申请号：US12719475
申请日：2010-03-08
申请人： Hiroshi OHTA , Wataru SAITO , Syotaro ONO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
发明人： Hiroshi OHTA , Wataru SAITO , Syotaro ONO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
IPC分类号： H01L27/06 , H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/7395 , H01L29/7813
摘要： A transistor contains a first semiconductor layer of a first conductivity type and a drift layer having a pillar structure in which a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type are alternately disposed in a direction parallel to a surface of the first semiconductor layer. The fourth semiconductor layer of the first conductivity type and the fifth semiconductor layer of the second conductivity type are alternately disposed and parallel to the drift layer. The fifth semiconductor layer has a larger amount of impurities than the fourth semiconductor layer. The sixth semiconductor layer of the first conductivity type and the seventh semiconductor layer of the second conductivity type are alternately disposed and parallel to the fourth and the fifth semiconductor layers. The seventh semiconductor layer has a smaller amount of impurities than the sixth semiconductor layer.
摘要翻译：晶体管包含第一导电类型的第一半导体层和具有柱结构的漂移层，其中第一导电类型的第二半导体层和第二导电类型的第三半导体层在平行于第一半导体层的表面。第一导电类型的第四半导体层和第二导电类型的第五半导体层交替地设置并平行于漂移层。第五半导体层的杂质量比第四半导体层大。第一导电类型的第六半导体层和第二导电类型的第七半导体层交替地设置并平行于第四和第五半导体层。第七半导体层的杂质量比第六半导体层少。

4. 发明授权

US08232593B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08232593B2
公开(公告)日：2012-07-31
申请号：US12714002
申请日：2010-02-26
申请人： Wataru Saito , Syotaro Ono , Hiroshi Ohta , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
发明人： Wataru Saito , Syotaro Ono , Hiroshi Ohta , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
IPC分类号： H01L29/78 , H01L29/06
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0649 , H01L29/0653 , H01L29/0661 , H01L29/0692 , H01L29/0696 , H01L29/407 , H01L29/7395 , H01L29/861 , H01L29/8611
摘要： A power semiconductor device according to an embodiment of the present invention includes a first semiconductor layer of a first or second conductivity type, a second semiconductor layer of the first conductivity type formed on the first semiconductor layer, a third semiconductor layer of the second conductivity type selectively formed on a surface of the second semiconductor layer, at least one trench formed in a periphery of the third semiconductor layer on the surface of the second semiconductor layer, a depth of a bottom surface of the at least one trench being deeper than a bottom surface of the third semiconductor layer, and shallower than a top surface of the first semiconductor layer, and some or all of the at least one trench being in contact with a side surface of the third semiconductor layer, at least one insulator buried in the at least one trench, a first main electrode electrically connected to the first semiconductor layer, and a second main electrode electrically connected to the third semiconductor layer.
摘要翻译：根据本发明实施例的功率半导体器件包括第一或第二导电类型的第一半导体层，形成在第一半导体层上的第一导电类型的第二半导体层，第二导电类型的第三半导体层选择性地形成在第二半导体层的表面上，形成在第二半导体层的表面上的第三半导体层的周边中的至少一个沟槽，至少一个沟槽的底表面的深度比底部表面，并且比第一半导体层的顶表面浅，并且至少一个沟槽的一些或全部与第三半导体层的侧表面接触，至少一个绝缘体埋在第三半导体层至少一个沟槽，与第一半导体层电连接的第一主电极和电连接的第二主电极引导到第三半导体层。

5. 发明授权

US08125023B2 Vertical type power semiconductor device having a super junction structure 有权
标题翻译：具有超结结构的垂直型功率半导体器件
公开(公告)号：US08125023B2
公开(公告)日：2012-02-28
申请号：US12620045
申请日：2009-11-17
申请人： Hiroshi Ohta , Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
发明人： Hiroshi Ohta , Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/7395 , H01L29/7811 , Y10S257/901
摘要： In a vertical power semiconductor device having the super junction structure both in a device section and a terminal section, an n-type impurity layer is formed on the outer peripheral surface in the super junction structure. This allows an electric field on the outer peripheral surface of the super junction structure region to be reduced. Accordingly, a reliable vertical power semiconductor device of a high withstand voltage can be provided.
摘要翻译：在器件部分和端子部分都具有超结结构的垂直功率半导体器件中，在超结结构的外周表面上形成n型杂质层。这允许减小超结结构区域的外周表面上的电场。因此，可以提供高耐受电压的可靠的垂直功率半导体器件。

6. 发明申请

US20110227154A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110227154A1
公开(公告)日：2011-09-22
申请号：US13052032
申请日：2011-03-18
申请人： Syotaro ONO , Wataru Saito , Munehisa Yabuzaki , Shunji Taniuchi , Miho Watanabe
发明人： Syotaro ONO , Wataru Saito , Munehisa Yabuzaki , Shunji Taniuchi , Miho Watanabe
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/66712
摘要： A semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type formed on the first semiconductor layer; a first buried layer of the first conductivity type selectively formed in the second semiconductor layer and having a first peak impurity concentration at a first depth; a second buried layer of a second conductivity type selectively formed in the second semiconductor layer and having a second peak impurity concentration at a second depth; a base layer of the second conductivity type selectively formed in the second semiconductor layer and overlapping with an upper portion of the second buried layer; a source layer of the first conductivity type selectively formed in the base layer; and a gate electrode formed on the base layer and on the second semiconductor layer above the first buried layer with a gate insulating film being interposed therebetween.
摘要翻译：一种半导体器件，包括：第一导电类型的第一半导体层; 形成在第一半导体层上的第一导电类型的第二半导体层; 第一导电类型的第一掩埋层选择性地形成在第二半导体层中，并且在第一深度处具有第一峰值杂质浓度; 第二导电类型的第二掩埋层选择性地形成在第二半导体层中，并且在第二深度具有第二峰值杂质浓度; 第二导电类型的基极层选择性地形成在第二半导体层中并与第二掩埋层的上部重叠; 选择性地形成在所述基底层中的所述第一导电类型的源极层; 以及形成在所述第一掩埋层上的所述基极层和所述第二半导体层上的栅电极，其间插入有栅极绝缘膜。

7. 发明申请

US20110215418A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110215418A1
公开(公告)日：2011-09-08
申请号：US13029925
申请日：2011-02-17
申请人： Wataru SAITO , Syotaro Ono , Munehisa Yabuzaki , Shunji Taniuchi , Miho Watanabe
发明人： Wataru SAITO , Syotaro Ono , Munehisa Yabuzaki , Shunji Taniuchi , Miho Watanabe
IPC分类号： H01L27/07 , H01L29/72
CPC分类号： H01L27/07 , H01L29/72
摘要： According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a first main electrode, a third semiconductor region of a second conductivity type, a second main electrode, and a plurality of embedded semiconductor regions of the second conductivity type. The second semiconductor region is formed on a first major surface of the first semiconductor region. The first main electrode is formed on a face side opposite to the first major surface of the first semiconductor region. The third semiconductor region is formed on a second major surface of the second semiconductor region on a side opposite to the first semiconductor region. The second main electrode is formed to bond to the third semiconductor region. The embedded semiconductor regions are provided in a termination region. A distance between the embedded semiconductor region and the second major surface along a direction from the second major surface toward the first major surface becomes longer toward outside from the device region.
摘要翻译：根据一个实施例，半导体器件包括第一导电类型的第一半导体区域，第一导电类型的第二半导体区域，第一主电极，第二导电类型的第三半导体区域，第二主电极和多个第二导电类型的嵌入式半导体区域。第二半导体区域形成在第一半导体区域的第一主表面上。第一主电极形成在与第一半导体区域的第一主表面相对的正面上。第三半导体区域形成在第二半导体区域的与第一半导体区域相对的一侧的第二主表面上。第二主电极形成为结合到第三半导体区域。嵌入式半导体区域设置在终端区域中。沿着从第二主表面朝向第一主表面的方向在嵌入式半导体区域和第二主表面之间的距离从器件区域向外部变长。

8. 发明申请

US20110018055A1 POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 失效
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US20110018055A1
公开(公告)日：2011-01-27
申请号：US12840201
申请日：2010-07-20
申请人： Hiroshi OHTA , Yasuto SUMI , Kiyoshi KIMURA , Wataru SEKINE , Wataru SAITO , Syotaro ONO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
发明人： Hiroshi OHTA , Yasuto SUMI , Kiyoshi KIMURA , Wataru SEKINE , Wataru SAITO , Syotaro ONO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66712 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/7811
摘要： According to one embodiment, a power semiconductor device includes a first semiconductor layer, and first, second and third semiconductor regions. The first semiconductor layer has a first conductivity type. The first semiconductor regions have a second conductivity type, and are formed with periodicity in a lateral direction in a second semiconductor layer of the first conductivity type. The second semiconductor layer is provided on a major surface of the first semiconductor layer in a device portion with a main current path formed in a vertical direction generally perpendicular to the major surface and in a terminal portion provided around the device portion. The second semiconductor region has the first conductivity type and is a portion of the second semiconductor layer sandwiched between adjacent ones of the first semiconductor regions. The third semiconductor regions have the second conductivity type and are provided below the first semiconductor regions in the terminal portion.
摘要翻译：根据一个实施例，功率半导体器件包括第一半导体层以及第一，第二和第三半导体区域。第一半导体层具有第一导电类型。第一半导体区域具有第二导电类型，并且在第一导电类型的第二半导体层中在横向方向上形成周期性。第二半导体层设置在器件部分的第一半导体层的主表面上，其主电流通道形成在大体上垂直于主表面的垂直方向上，以及设置在器件部分周围的端子部分中。第二半导体区域具有第一导电类型，并且是夹在相邻的第一半导体区域中的第二半导体层的一部分。第三半导体区域具有第二导电类型并且设置在端子部分中的第一半导体区域的下方。

9. 发明授权

US08610210B2 Power semiconductor device and method for manufacturing same 失效
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US08610210B2
公开(公告)日：2013-12-17
申请号：US12840201
申请日：2010-07-20
申请人： Hiroshi Ohta , Yasuto Sumi , Kiyoshi Kimura , Wataru Sekine , Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
发明人： Hiroshi Ohta , Yasuto Sumi , Kiyoshi Kimura , Wataru Sekine , Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
IPC分类号： H01L29/66
CPC分类号： H01L29/66712 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/7811
摘要： According to one embodiment, a power semiconductor device includes a first semiconductor layer, and first, second and third semiconductor regions. The first semiconductor layer has a first conductivity type. The first semiconductor regions have a second conductivity type, and are formed with periodicity in a lateral direction in a second semiconductor layer of the first conductivity type. The second semiconductor layer is provided on a major surface of the first semiconductor layer in a device portion with a main current path formed in a vertical direction generally perpendicular to the major surface and in a terminal portion provided around the device portion. The second semiconductor region has the first conductivity type and is a portion of the second semiconductor layer sandwiched between adjacent ones of the first semiconductor regions. The third semiconductor regions have the second conductivity type and are provided below the first semiconductor regions in the terminal portion.
摘要翻译：根据一个实施例，功率半导体器件包括第一半导体层以及第一，第二和第三半导体区域。第一半导体层具有第一导电类型。第一半导体区域具有第二导电类型，并且在第一导电类型的第二半导体层中在横向方向上形成周期性。第二半导体层设置在器件部分的第一半导体层的主表面上，其主电流通道形成在大体上垂直于主表面的垂直方向上，以及设置在器件部分周围的端子部分中。第二半导体区域具有第一导电类型，并且是夹在相邻的第一半导体区域中的第二半导体层的一部分。第三半导体区域具有第二导电类型并且设置在端子部分中的第一半导体区域的下方。

10. 发明授权

US08188521B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08188521B2
公开(公告)日：2012-05-29
申请号：US12728823
申请日：2010-03-22
申请人： Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
发明人： Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
IPC分类号： H01L29/739 , H01L29/78 , H01L29/08
CPC分类号： H01L29/7802 , H01L29/0619 , H01L29/0626 , H01L29/0634 , H01L29/0657 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/7808 , H01L29/7811 , H01L29/7828
摘要： A power semiconductor device has semiconductor layers, including: first layer of first type; second and third layers respectively of first and second types alternately on the first layer; fourth layers of second type on the third layers; fifth layers of first type on the fourth layer; sixth and seventh layers respectively of second and first types alternately on the second and third layers; a first electrode connected to the first layer; an insulation film on fourth, sixth, and seventh layers; a second electrode on fourth, sixth, and seventh layers via the insulation film; and a third electrode joined to fourth and fifth layers, wherein the sixth layers are connected to the fourth layers and one of the third layers between two fourth layers, and an impurity concentration of the third layers below the sixth layers is higher than that of the third layers under the fourth layers.
摘要翻译：功率半导体器件具有半导体层，包括：第一层第一层; 第一和第二类型的第二和第三层交替地在第一层上; 第三层第四层第四层; 第四层第五层第一层; 第二层和第三层的第六层和第七层交替地在第二层和第三层上; 连接到第一层的第一电极; 第四层，第六层和第七层的绝缘膜; 经由绝缘膜的第四，第六和第七层上的第二电极; 以及连接到第四和第五层的第三电极，其中第六层连接到第四层，第二层之间的第三层之间的第二层之间的第二层和第三层之间的第三层的杂质浓度高于第六层的第三层第四层第三层。

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