会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明授权
    • Synchronous counter
    • 同步计数器
    • US5526393A
    • 1996-06-11
    • US405152
    • 1995-03-16
    • Mitsuaki KondoTakamoto Watanabe
    • Mitsuaki KondoTakamoto Watanabe
    • H03K23/00H03K23/40H03K23/50H03K21/02
    • H03K23/50
    • A synchronous counter comprises one D flip-flop circuit for performing divide-by-2 frequency division of a clock signal CK, JK flip-flop circuits for, when input signals have HIGH levels (logical value 1), inverting the levels of the output signals in synchronization with the clock signal CK, logic circuits for inputting control signals to the JK flip-flop circuits, lower-stage signal assembling circuits for grouping the output signals from the JK flip-flop circuits into two-signal-unit groups to produce logical product signals of the signals in these two,signal-unit groups, and upper-stage signal assembling circuits for further handling the output signals from the lower-stage signal assembling circuits, thereby firstly simultaneously satisfying an increase in speed of the counting operation as well as simplification of the wiring pattern and reduction in the circuit area and secondly realizing further increase in the counting operation.
    • 同步计数器包括一个D触发器电路,用于在输入信号具有高电平(逻辑值1)时执行时钟信号CK的二分频分频,JK触发器电路,使输出的电平反相 与时钟信号CK同步的信号,用于向JK触发器电路输入控制信号的逻辑电路,用于将来自JK触发器电路的输出信号分组为双信号单元组的下级信号组合电路,以产生 这两个信号单元组中的信号的逻辑积信号和用于进一步处理来自下级信号组合电路的输出信号的上级信号组合电路,从而首先同时满足计数操作的速度增加,如 以及布线图案的简化和电路面积的缩小,二次实现计数操作的进一步增加。