专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06319787B1 Method for forming a high surface area trench capacitor 失效
标题翻译：高表面积沟槽电容器的形成方法
公开(公告)号：US06319787B1
公开(公告)日：2001-11-20
申请号：US09107980
申请日：1998-06-30
申请人： Gerhard Enders , Matthias Ilg , Dietrich Widmann
发明人： Gerhard Enders , Matthias Ilg , Dietrich Widmann
IPC分类号： H01L2120
CPC分类号： H01L27/10861 , H01L27/10829
摘要： A trench capacitor having a substrate with a trench extending therein with a nested, e.g., concentric, conductive regions disposed within the trench. A dielectric material is disposed within the substrate. The dielectric material has portions thereof disposed between the concentric conductive regions to dielectrically electrically separate one of the conductive regions from another one of the conductive regions. The dielectrically separated conductive regions provide a pair of electrodes for the capacitor. Selected ones of the concentric conductive regions are electrically connected to provide one of the electrodes for the capacitor. The substrate has a conductive region therein and one of the concentric conductive regions providing one of the electrodes is electrically connected to the conductive region in the substrate. One of the concentric conductive regions is electrically connected to a conductive region in the substrate through a bottom portion of the trench.
摘要翻译：一种沟槽式电容器，其具有在其中延伸有沟槽的衬底，其具有设置在沟槽内的嵌套的，例如同心的导电区域。电介质材料设置在衬底内。电介质材料具有设置在同心导电区域之间的部分，以将导电区域中的一个与另一个导电区域电介质电分离。介电分离的导电区域为电容器提供一对电极。选择的同心导电区域被电连接以提供用于电容器的电极之一。衬底在其中具有导电区域，并且提供电极之一的同心导电区域中的一个电连接到衬底中的导电区域。一个同心导电区域通过沟槽的底部电连接到衬底中的导电区域。

2. 发明授权

US5807792A Uniform distribution of reactants in a device layer 失效
标题翻译：反应物在器件层中的均匀分布
公开(公告)号：US5807792A
公开(公告)日：1998-09-15
申请号：US768826
申请日：1996-12-18
申请人： Matthias Ilg , Markus Kirchhoff , Christoph Werner
发明人： Matthias Ilg , Markus Kirchhoff , Christoph Werner
IPC分类号： H01L21/683 , C23C16/44 , C23C16/455 , C30B25/14 , H01L21/205 , H01L21/31 , H01L21/316
CPC分类号： H01L21/02271 , C23C16/44 , C23C16/455 , C30B25/14 , H01L21/02129 , H01L21/31625
摘要： A method and apparatus for forming a multi-constituent device layer on a wafer surface are disclosed. The multi-constituent device layer is formed by flowing a first chemistry comprising a first constituent and a second chemistry comprising a second constituent via a segmented delivery system into a reaction chamber. The reaction chamber comprises a susceptor for supporting and rotating the wafers. The segmented delivery system comprises alternating first and second segments into which the first and second chemistries, respectively, are flowed. The first segments comprise an area that is greater than an area of the second segments by an amount sufficient to effectively reduce the diffusion path of the first constituent. Reducing the diffusion path of the first constituent results in a more uniform distribution of the first constituent within the device layer.
摘要翻译：公开了一种用于在晶片表面上形成多组分器件层的方法和装置。通过将包含第一组分的第一化学物质和包含第二组分的第二化学物质通过分段递送系统流入反应室而形成多构成器件层。反应室包括用于支撑和旋转晶片的基座。分段递送系统包括交替的第一和第二段，第一和第二化学物质分别流入其中。第一段包括大于第二段的面积的面积，其量足以有效地减小第一组分的扩散路径。降低第一组分的扩散路径导致第一组分在器件层内的更均匀分布。

3. 发明授权

US5753948A Advanced damascene planar stack capacitor fabrication method 失效
公开(公告)号：US5753948A
公开(公告)日：1998-05-19
申请号：US752137
申请日：1996-11-19
申请人： Son Van Nguyen , Matthias Ilg , Kevin J. Uram
发明人： Son Van Nguyen , Matthias Ilg , Kevin J. Uram
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L29/72
CPC分类号： H01L27/1085 , H01L28/87
摘要： Capacitor storage charge can be increased by increasing storage node area. A high aspect surface ratio stack capacitor is produced without increasing overall cell dimensions. The node is formed with layers of low doped and high doped concentration borophosphosilicate glass which is deposited by a single process step with precise nanometer dimensions, are selectively etched so that either doped or undoped layers will have a higher etch rate. This etching creates finger-like projections in the node, which provide for greater surface area using a very simplified process requiring fewer processing steps.

4. 发明授权

US06492282B1 Integrated circuits and manufacturing methods 失效
标题翻译：集成电路和制造方法
公开(公告)号：US06492282B1
公开(公告)日：2002-12-10
申请号：US08846925
申请日：1997-04-30
申请人： Dirk Tobben , Peter Weigand , Matthias Ilg
发明人： Dirk Tobben , Peter Weigand , Matthias Ilg
IPC分类号： H01L21316
CPC分类号： H01L21/31051 , H01L21/76801 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76837
摘要： A method of filling gaps between adjacent gate electrodes of a semiconductor structure. A self-planarizing material is deposited over the structure. A first portion of such material flow between the gate electrode to fill the gaps and a second portion of such material becomes deposited over tops of the gate electrodes and over the gaps to form a layer with a substantially planar surface. A phosphorous dopant is formed in the second portion of the self-planarizing material. Thus, relatively small gaps may be filled effectively with a layer having a very planar surface for subsequent photolithography. The phosphorous dopant provides gettering to remove adverse effects of alkali contaminant ions which may enter the gap filling material. The dielectric constant of the material filing the gaps, i.e., the first portion of the gap filling material, being substantially free of such contaminants, has a relatively low dielectric constant thereby reducing electrical coupling between adjacent electrodes. The self-planarizing material is a flowable material. The flowable oxide may be spun on or may be deposited by gaseous deposition. The phosphorous dopant may be provided by, for example: implanting phosphorous ions into the second portion of the self-planarizing layer and heating the material to both cure such material and activate the phosphorous ions; depositing a phosphorous doped layer over the layer of self-planarizing material, heating the structure to out-diffuse the phosphorous dopant into the second portion of the self-planarizing material and selectively removing the deposited layer; or by curing the spun-on self-planarizing material in a phosphine environment.
摘要翻译：一种在半导体结构的相邻栅电极之间填充间隙的方法。在该结构上沉积自平面化材料。这种材料的第一部分在栅极电极之间流动以填充间隙，并且这种材料的第二部分沉积在栅电极的顶部上并在间隙上沉积以形成具有基本平坦表面的层。在自平面化材料的第二部分中形成磷掺杂剂。因此，可以用具有非常平坦的表面的层有效地填充相对小的间隙用于随后的光刻。磷掺杂剂提供吸气以除去可能进入间隙填充材料的碱性污染物离子的不利影响。填充间隙的材料的介电常数，即间隙填充材料的第一部分基本上没有这种污染物，具有相对低的介电常数，从而减少相邻电极之间的电耦合。自平面化材料是可流动的材料。可流动的氧化物可以通过气相沉积或在其上沉积。磷掺杂剂可以通过例如：将磷离子注入到自平坦化层的第二部分中并加热材料以固化这种材料并激活磷离子来提供磷掺杂剂; 在所述自平面化材料层上沉积磷掺杂层，加热所述结构以将所述磷掺杂剂扩散到所述自平面化材料的第二部分中并选择性地去除所述沉积层; 或通过在磷化氢环境中固化纺丝自平面化材料。

5. 发明授权

US06190955B1 Fabrication of trench capacitors using disposable hard mask 失效
标题翻译：使用一次性硬掩模制作沟槽电容器
公开(公告)号：US06190955B1
公开(公告)日：2001-02-20
申请号：US09014433
申请日：1998-01-27
申请人： Matthias Ilg , Richard L. Kleinhenz , Soichi Nadahara , Ronald W. Nunes , Klaus Penner , Klaus Roithner , Radhika Srinivasan , Shigeki Sugimoto
发明人： Matthias Ilg , Richard L. Kleinhenz , Soichi Nadahara , Ronald W. Nunes , Klaus Penner , Klaus Roithner , Radhika Srinivasan , Shigeki Sugimoto
IPC分类号： H01L218244
CPC分类号： H01L21/3081
摘要： Improved trench forming methods for semiconductor substrates using BSG avoid the problems associated with conventional TEOS hard mask techniques. The methods comprise: (a) providing a semiconductor substrate, (b) applying a conformal layer of borosilicate glass (BSG) on the substrate; (c) forming a patterned photoresist layer over the BSG layer whereby a portion of a layer underlying the photoresist layer is exposed, (d) anisotropically etching through the exposed portion of the underlying layer, through any other layers lying between the photoresist layer and the semiconductor substrate, and into the semiconductor substrate, thereby forming a trench in the semiconductor substrate. Preferably, one or more dielectric layers are present on the substrate surface prior to application of the BSG layer. One or more chemical barrier and/or organic antireflective coating layers may be applied over the BSG layer between the BSG layer and the photoresist layer. The methods are especially useful for forming deep trenches in silicon substrates with pad dielectric layers.
摘要翻译：使用BSG的半导体衬底的改进的沟槽形成方法避免了与常规TEOS硬掩模技术相关的问题。所述方法包括：（a）提供半导体衬底，（b）在衬底上施加保形层硼硅酸盐玻璃（BSG）;（c）在BSG层上形成图案化的光刻胶层，由此在光刻胶下面的一部分层（d）通过位于光致抗蚀剂层和半导体衬底之间的任何其它层，通过底层的暴露部分进行各向异性蚀刻，并进入半导体衬底，由此在半导体衬底中形成沟槽。优选地，一个或更多的介电层在施加BSG层之前存在于衬底表面上。可以在BSG层和光致抗蚀剂层之间的BSG层上施加一个或多个化学屏障和/或有机抗反射涂层。该方法对于在具有焊盘电介质层的硅衬底中形成深沟槽特别有用。

6. 发明授权

US6130145A Insitu doped metal policide 失效
标题翻译：天然掺杂金属防腐剂
公开(公告)号：US6130145A
公开(公告)日：2000-10-10
申请号：US10081
申请日：1998-01-21
申请人： Matthias Ilg , Johnathan Faltermeier , Radhika Srinivasan
发明人： Matthias Ilg , Johnathan Faltermeier , Radhika Srinivasan
IPC分类号： H01L21/28 , H01L21/8242 , H01L27/108 , H01L29/49 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/4933 , H01L21/28061
摘要： A reduced metal-rich interface between a poly and metal silicide layer is achieved by insitu doping the metal silicide layer.
摘要翻译：多金属硅化物层和金属硅化物层之间还原的富金属界面通过掺杂金属硅化物层来实现。

7. 发明授权

US5935873A Deposition of carbon into nitride layer for improved selectivity of oxide to nitride etchrate for self aligned contact etching 失效
标题翻译：将碳沉积到氮化物层中，以提高氧化物对氮化物蚀刻的选择性，用于自对准接触蚀刻
公开(公告)号：US5935873A
公开(公告)日：1999-08-10
申请号：US939148
申请日：1997-09-29
申请人： Bruno Spuler , Juergen Wittmann , Martin Gutsche , Wolfgang Bergner , Matthias Ilg
发明人： Bruno Spuler , Juergen Wittmann , Martin Gutsche , Wolfgang Bergner , Matthias Ilg
IPC分类号： H01L21/28 , H01L21/265 , H01L21/302 , H01L21/318 , H01L21/3213 , H01L21/60 , C23C14/00 , C23C14/48
CPC分类号： H01L21/76897 , H01L21/3185
摘要： A method for forming a Self Aligned Contact in a semiconductor device includes incorporating carbon into a nitride layer during or following the formation of the nitride layer on a semiconductor substrate.
摘要翻译：在半导体器件中形成自对准接触的方法包括在半导体衬底上形成氮化物层期间或之后将碳结合到氮化物层中。

8. 发明授权

US5770469A Method for forming semiconductor structure using modulation doped silicate glasses 失效
标题翻译：使用调制掺杂硅酸盐玻璃形成半导体结构的方法
公开(公告)号：US5770469A
公开(公告)日：1998-06-23
申请号：US578165
申请日：1995-12-29
申请人： Kevin J. Uram , John K. Shugrue , Nathan P. Sandler , Son Van Nguyen , Matthias Ilg
发明人： Kevin J. Uram , John K. Shugrue , Nathan P. Sandler , Son Van Nguyen , Matthias Ilg
IPC分类号： C23C16/40 , C23C16/44 , C23C16/455 , C23C16/50 , H01L21/316 , H01L21/768 , H01L23/29
CPC分类号： C23C16/45523 , C23C16/401 , C23C16/45508 , C23C16/50 , H01L21/02126 , H01L21/02129 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31608 , H01L21/76837 , H01L23/291 , H01L2924/0002 , Y10S438/982
摘要： A method of fabricating a semiconductor structure utilizing doped silicate glass on a substrate of a wafer. The method includes the step forming a modulation doped silicate glass structure over a first layer of the wafer. The modulation doped silicate glass structure is formed by depositing at least two alternating layers of heavily-doped silicate glass and lightly-doped silicate glass over the first layer. Both the heavily-doped silicate glass and lightly-doped silicate glass layers may comprise glass doped with both a first dopant and a second dopant. The first dopant may represent, for example, phosphorous, and the second dopant may represent, for example, boron.
摘要翻译：一种在晶片的衬底上制造利用掺杂的硅酸盐玻璃的半导体结构的方法。该方法包括在晶片的第一层上形成调制掺杂硅酸盐玻璃结构的步骤。调制掺杂硅酸盐玻璃结构通过在第一层上沉积至少两层重掺杂硅酸盐玻璃和轻掺杂硅酸盐玻璃的交替层而形成。重掺杂的硅酸盐玻璃和轻掺杂的硅酸盐玻璃层可以包括掺杂有第一掺杂剂和第二掺杂剂的玻璃。第一掺杂剂可以表示例如磷，第二掺杂剂可以表示例如硼。

9. 发明授权

US06197666B1 Method for the fabrication of a doped silicon layer 有权
标题翻译：掺杂硅层的制造方法
公开(公告)号：US06197666B1
公开(公告)日：2001-03-06
申请号：US09390496
申请日：1999-09-03
申请人： Herbert Schafer , Martin Franosch , Reinhard Stengl , Hans Reisinger , Matthias Ilg
发明人： Herbert Schafer , Martin Franosch , Reinhard Stengl , Hans Reisinger , Matthias Ilg
IPC分类号： H01L2120
CPC分类号： H01L27/10873 , C23C16/24 , C23C16/56 , H01L21/28035 , H01L21/32055 , H01L21/76877
摘要： A method for the fabrication of a doped silicon layer, includes carrying out deposition by using a process gas containing SiH4, Si2H6 and a doping gas. The doped silicon layer which is thus produced can be used both as a gate electrode of an MOS transistor and as a conductive connection. At a thickness between 50 and 200 nm it has a resistivity less than or equal to 0.5 m&OHgr;cm.
摘要翻译：一种用于制造掺杂硅层的方法，包括通过使用含有SiH 4，Si 2 H 6和掺杂气体的工艺气体进行沉积。由此制造的掺杂硅层既可以用作MOS晶体管的栅电极，也可以用作导电连接。在50至200nm的厚度之间，其电阻率小于或等于0.5mOMEGAcm。

10. 发明授权

US6096654A Gapfill of semiconductor structure using doped silicate glasses 失效
标题翻译：使用掺杂硅酸盐玻璃的半导体结构的填隙
公开(公告)号：US6096654A
公开(公告)日：2000-08-01
申请号：US942273
申请日：1997-09-30
申请人： Markus M. Kirchhoff , Matthias Ilg
发明人： Markus M. Kirchhoff , Matthias Ilg
IPC分类号： H01L21/316 , H01L21/762 , H01L21/768 , H01L23/522 , H01L21/302
CPC分类号： H01L21/76229 , H01L21/76837
摘要： Improved gap fill of narrow spaces is achieved by using a doped silicate glass having a dopant concentration in a bottom portion thereof which is greater than an amount which causes surface crystal growth and in an upper portion thereof having a lower dopant concentration such that the overall dopant concentration of the doped silicate glass is below that which causes surface crystal growth.
摘要翻译：通过使用其底部中的掺杂剂浓度大于引起表面晶体生长的量的掺杂硅酸盐玻璃和其掺杂浓度较低的上部，使得全部掺杂剂掺杂硅酸盐玻璃的浓度低于引起表面晶体生长的浓度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式