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1. 发明申请

US20120034706A1 METHOD FOR ASSESSING INFLAMMATORY CONDITION 审中-公开
标题翻译：评估炎症条件的方法
公开(公告)号：US20120034706A1
公开(公告)日：2012-02-09
申请号：US12964077
申请日：2010-12-09
申请人： Yukitaka Ueki , Nobuhito Masuda , Kyoko Miyamoto , Chihiro Miyazawa , Yukio Sudo
发明人： Yukitaka Ueki , Nobuhito Masuda , Kyoko Miyamoto , Chihiro Miyazawa , Yukio Sudo
IPC分类号： G01N33/53
CPC分类号： G01N33/6893 , G01N2333/4737 , G01N2800/102
摘要： Provided a method for correctly assessing an inflammatory condition of a patient who is receiving a therapy with an IL-6 inhibitor. The method for assessing an inflammatory condition of a patient who is receiving an IL-6 inhibitor, including determining a PTX3 level of a sample derived from a patient who is receiving an IL-6 inhibitor.
摘要翻译：提供了正确评估接受IL-6抑制剂治疗的患者的炎症状态的方法。用于评估正在接受IL-6抑制剂的患者的炎症状态的方法，包括确定来自接受IL-6抑制剂的患者的样品的PTX3水平。

2. 发明授权

US6143609A Method for forming semiconductor memory device 失效
标题翻译：半导体存储器件形成方法
公开(公告)号：US6143609A
公开(公告)日：2000-11-07
申请号：US824476
申请日：1996-12-02
申请人： Kazuo Sato , Kenji Ueda , Michio Morita , Fumihiko Noro , Kyoko Miyamoto , Hideaki Onishi , Kazuo Umeda , Kazuya Kubo
发明人： Kazuo Sato , Kenji Ueda , Michio Morita , Fumihiko Noro , Kyoko Miyamoto , Hideaki Onishi , Kazuo Umeda , Kazuya Kubo
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： A floating gate type semiconductor memory and method of manufacture are described including an erasing gate electrode in which a tunneling region can be formed easily and high reliability can be kept. An active region isolated by element isolation insulating films is formed on a semiconductor substrate. A gate insulating film and a floating gate electrode are sequentially formed on the active region. A control gate electrode is formed above the floating gate electrode with a silicon oxide film disposed therebetween. A tunneling insulating film is formed only on the side wall of the floating gate electrode. Then, an erasing gate electrode is formed so as to cover the tunneling insulating film.
摘要翻译：描述了浮栅型半导体存储器及其制造方法，其特征在于包括能够容易地形成隧道区域的擦除栅极电极，并且可以保持高的可靠性。在半导体衬底上形成由元件隔离绝缘膜隔离的有源区。在有源区上依次形成栅极绝缘膜和浮栅电极。在浮置栅电极的上方形成有控制栅电极，其间配置有氧化硅膜。隧道绝缘膜只形成在浮栅电极的侧壁上。然后，形成擦除栅电极以覆盖隧道绝缘膜。

3. 发明授权

US5951879A Method of etching polysilicon layer 失效
标题翻译：蚀刻多晶硅层的方法
公开(公告)号：US5951879A
公开(公告)日：1999-09-14
申请号：US631003
申请日：1996-04-12
申请人： Kyoko Miyamoto , Satoshi Nakagawa
发明人： Kyoko Miyamoto , Satoshi Nakagawa
IPC分类号： H05H1/46 , C23F4/00 , H01L21/302 , H01L21/3065 , H01L21/3213 , H01L29/78 , H01L2/302
CPC分类号： H01L21/32137
摘要： A highly reliable semiconductor IC circuit can be produced by this etching method: A resist layer is formed on a polysilicon layer which is formed on a silicon dioxide layer on a silicon substrate. The resist layer is used as a mask, and silicon oxide layer deposits thereon while polysilicon layer is being etched. Carbon emission out of the resist layer is thus restrained, and thereby a selectivity, an etching speed ratio of polysilicon layer vs. silicon dioxide layer, is substantially raised.
摘要翻译：可以通过该蚀刻方法制造高可靠性的半导体IC电路：在形成于硅衬底上的二氧化硅层上的多晶硅层上形成抗蚀剂层。抗蚀剂层用作掩模，并且氧化硅层沉积在其上，同时蚀刻多晶硅层。因此抑制了抗蚀剂层中的碳发射，从而大大提高了多晶硅层与二氧化硅层的选择性，蚀刻速度比。

4. 发明授权

US5838039A Semiconductor memory having a tunneling region 失效
标题翻译：具有隧道区域的半导体存储器
公开(公告)号：US5838039A
公开(公告)日：1998-11-17
申请号：US677651
申请日：1996-07-08
申请人： Kazuo Sato , Kenji Ueda , Michio Morita , Fumihiko Noro , Kyoko Miyamoto , Hideaki Onishi , Kazuo Umeda , Kazuya Kubo
发明人： Kazuo Sato , Kenji Ueda , Michio Morita , Fumihiko Noro , Kyoko Miyamoto , Hideaki Onishi , Kazuo Umeda , Kazuya Kubo
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L29/78 , H01L21/265
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： A floating gate type semiconductor memory and method of manufacture are described including an erasing gate electrode in which a tunneling region can be formed easily and high reliability can be kept. An active region isolated by element isolation insulating films is formed on a semiconductor substrate. A gate insulating film and a floating gate electrode are sequentially formed on the active region. A control gate electrode is formed above the floating gate electrode with a silicon oxide film disposed therebetween. A tunneling insulating firm is formed only on the side wall of the floating gate electrode. Then, an erasing gate electrode is formed so as to cover the tunneling insulating film.
摘要翻译：描述了浮栅型半导体存储器及其制造方法，其特征在于包括能够容易地形成隧道区域的擦除栅极电极，并且可以保持高的可靠性。在半导体衬底上形成由元件隔离绝缘膜隔离的有源区。在有源区上依次形成栅极绝缘膜和浮栅电极。在浮置栅电极的上方形成有控制栅电极，其间配置有氧化硅膜。仅在浮栅电极的侧壁上形成隧道绝缘固体。然后，形成擦除栅电极以覆盖隧道绝缘膜。

5. 发明授权

US07857013B2 Method for producing carbon fiber woven fabric 有权
标题翻译：生产碳纤维织物的方法
公开(公告)号：US07857013B2
公开(公告)日：2010-12-28
申请号：US12298396
申请日：2007-04-27
申请人： Eisuke Wadahara , Ikuo Horibe , Shigeru Miyamoto , Kyoko Miyamoto, legal representative , Kenichi Takezawa , Kuniyoshi Kurihara , Kazuhiro Ohno
发明人： Eisuke Wadahara , Ikuo Horibe , Shigeru Miyamoto , Kenichi Takezawa , Kuniyoshi Kurihara , Kazuhiro Ohno
IPC分类号： D03D41/00 , D03D13/00 , D03D25/00
CPC分类号： D03D47/3053 , D03D15/0094 , D03D49/04 , D10B2101/12 , Y10S139/01
摘要： The present invention has an object of providing a method for producing a carbon fiber woven fabric in which the length of each warp yarn made of a carbon fiber strand is uniform, weft yarns are straightly arranged without waviness, and that is excellent in quality can be obtained with high productivity (production speed), and is characterized that a method for producing a carbon fiber woven fabric using an air jet loom in which heald in a shedding motion has an angle of repose in a range of 0 to 50° when weaving a uni-directional carbon fiber woven fabric woven with a carbon fiber strand having a fineness of 400 to 6,000 tex as the warp yarn and an auxiliary fiber having a fineness of ⅕ or less of the carbon fiber strand as the weft yarn.
摘要翻译：本发明的目的是提供一种碳纤维织物的制造方法，其中由碳纤维股线制成的每根经纱的长度均匀，纬纱直线布置而没有波纹，质量优异的可以是以生产率高（生产速度）获得，其特征在于，使用喷气织机制造碳纤维织物的方法，其中，当织造a时，在脱落运动中综合的角度为0至50° 用作为经纱的细度为400〜6000tex的碳纤维线和作为纬纱的碳纤维线的细度为⅕以下的辅助纤维编织的单向碳纤维织物。

6. 发明授权

US5491101A Manufacturing method of non-volatile semiconductor memory devices 失效
标题翻译：非易失性半导体存储器件的制造方法
公开(公告)号：US5491101A
公开(公告)日：1996-02-13
申请号：US348100
申请日：1994-11-25
申请人： Kyoko Miyamoto , Fumihiko Noro
发明人： Kyoko Miyamoto , Fumihiko Noro
IPC分类号： H01L21/336 , H01L27/115 , H01L21/8247
CPC分类号： H01L29/66825 , H01L27/115
摘要： The invention provides a process to form on a certain conductive type semiconductor substrate 1 insulation layer 9 having openings 11, which regions will become source and drain; a process to form diffusion layer 8 of the same conductive type as semiconductor substrate 1 in to-be-drain space, with insulation layer 9 and photoresist 10 as masks; a process to form side wall layer 13 alongside openings of insulation layer 9; a process to form diffusion layers 4 and 5, conductive type of which layers is opposite to that of semiconductor substrate 1, in to-be-source and to-be-drain regions, with insulation layer 9 and side wall layer 13 as masks; a process to remove insulation layer 9 and side wall layer 13; and a process to form insulation layer 2 on semiconductor substrate in channel region distinguished by, and including part of, diffusion layers 4 and 5, and to form floating-gate electrode 3 on insulation layer 2, and control-gate electrode 7 with insulation layer 6 in between. The manufacturing method according to this invention forms drain and high density P-type diffusion layer by making use of side wall layer. Therefore, this makes it possible to shape DSA structure controlling the distance from drain to high density P-type diffusion layer with high accuracy, without using high temperature diffusion process. This means that this invention offers an easy way to make DSA structure with finer design rules.
摘要翻译：本发明提供一种在具有开口11的某种导电型半导体衬底1绝缘层9上形成的工艺，该区域将成为源极和漏极; 形成与待漏极空间中的半导体衬底1相同的导电类型的扩散层8的工艺，绝缘层9和光致抗蚀剂10作为掩模; 沿着绝缘层9的开口形成侧壁层13的工艺; 形成扩散层4和5的工艺，其导电类型的层与半导体衬底1的导电类型在源极和漏极区域中，绝缘层9和侧壁层13作为掩模; 去除绝缘层9和侧壁层13的工艺; 以及在由扩散层4和5区分并包括部分扩散层4和5的沟道区域中的半导体衬底上形成绝缘层2并在绝缘层2上形成浮栅电极3的绝缘层2和具有绝缘层的控制栅电极7的工艺 6之间。根据本发明的制造方法通过利用侧壁层形成漏极和高密度P型扩散层。因此，能够在不使用高温扩散处理的情况下，高精度地形成控制从漏极到高密度P型扩散层的距离的DSA结构。这意味着本发明提供了使DSA结构具有更精细的设计规则的简单方法。

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