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1. 发明授权

US07075365B1 Configurable clock network for programmable logic device 失效
公开(公告)号：US07075365B1
公开(公告)日：2006-07-11
申请号：US10830562
申请日：2004-04-22
申请人： Gregory Starr , Kang Wei Lai , Richard Y. Chang
发明人： Gregory Starr , Kang Wei Lai , Richard Y. Chang
IPC分类号： H01L25/00
CPC分类号： H03K19/017581 , G06F1/10
摘要： In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.

2. 发明授权

US08441314B1 Configurable clock network for programmable logic device 有权
标题翻译：可编程逻辑器件的可配置时钟网络
公开(公告)号：US08441314B1
公开(公告)日：2013-05-14
申请号：US13558904
申请日：2012-07-26
申请人： Gregory Starr , Kang Wei Lai , Richard Y. Chang
发明人： Gregory Starr , Kang Wei Lai , Richard Y. Chang
IPC分类号： H01L25/00
CPC分类号： H03K19/017581 , G06F1/10
摘要： In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.
摘要翻译：在具有高速串行接口通道的可编程逻辑器件中，用于向这些高速串行接口的动态相位对准电路提供一个或多个高速时钟的时钟分配网络包括至少一个可分段的总线（例如使用可调缓冲区）。这允许总线在高速串行接口以不同的速度运行时被分成不同的部分，可以连接到不同的时钟源。在一个实施例中，分段元件（例如，上述缓冲器）位于所选择的通道（例如，每第四通道）之间，限制不同段的大小。在另一个实施例中，分段元件位于每个通道之间，允许完全用户在选择段的大小时的自由度。因此，代替为每个时钟源提供总线，通过分割单个总线，可以使多个时钟可用于不同的通道。

3. 发明授权

US08072260B1 Configurable clock network for programmable logic device 有权
标题翻译：可编程逻辑器件的可配置时钟网络
公开(公告)号：US08072260B1
公开(公告)日：2011-12-06
申请号：US12951486
申请日：2010-11-22
申请人： Gregory Starr , Kang Wei Lai , Richard Y. Chang
发明人： Gregory Starr , Kang Wei Lai , Richard Y. Chang
IPC分类号： H01L25/00
CPC分类号： H03K19/017581 , G06F1/10
摘要： In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.
摘要翻译：在具有高速串行接口通道的可编程逻辑器件中，用于向这些高速串行接口的动态相位对准电路提供一个或多个高速时钟的时钟分配网络包括至少一个可分段的总线（例如使用可调缓冲区）。这允许总线在高速串行接口以不同的速度运行时被分成不同的部分，可以连接到不同的时钟源。在一个实施例中，分段元件（例如，上述缓冲器）位于所选择的通道（例如，每第四通道）之间，限制不同段的大小。在另一个实施例中，分段元件位于每个通道之间，允许完全用户在选择段的大小时的自由度。因此，代替为每个时钟源提供总线，通过分割单个总线，可以使多个时钟可用于不同的通道。

4. 发明授权

US07602255B1 Loop circuits that reduce bandwidth variations 有权
标题翻译：减少带宽变化的环路电路
公开(公告)号：US07602255B1
公开(公告)日：2009-10-13
申请号：US11861144
申请日：2007-09-25
申请人： Kang-Wei Lai , Ninh D. Ngo , Kazi Asaduzzaman , Mian Z. Smith , Wanli Chang , Tim Tri Hoang
发明人： Kang-Wei Lai , Ninh D. Ngo , Kazi Asaduzzaman , Mian Z. Smith , Wanli Chang , Tim Tri Hoang
IPC分类号： H03L7/00
CPC分类号： H03L7/0895 , H03L7/0812
摘要： A feedback loop, such as a phase-locked loop, on an integrated circuit has a detector, a charge pump, and a loop filter. The charge pump adjusts its output current in response to variations in a process of the integrated circuit to reduce variations in the loop bandwidth. The charge pump also adjusts its output current in response to variations in a resistance of a resistor in the loop filter to reduce variations in the loop bandwidth. The charge pump can also adjust its output current in response to variations in a temperature of the integrated circuit to reduce variations in the loop bandwidth. A delay-locked loop on an integrated circuit has a phase detector and a charge pump. The charge pump adjusts its output current in response to variations in the temperature and the process of the integrated circuit to reduce changes in the loop bandwidth.
摘要翻译：在集成电路上的反馈回路（例如锁相环）具有检测器，电荷泵和环路滤波器。电荷泵响应于集成电路的过程中的变化来调节其输出电流，以减少环路带宽的变化。电荷泵还响应于环路滤波器中的电阻器的电阻的变化来调整其输出电流，以减少环路带宽的变化。电荷泵还可以响应于集成电路的温度变化来调节其输出电流，以减少环路带宽的变化。集成电路上的延迟锁定环路具有相位检测器和电荷泵。电荷泵响应于集成电路的温度和过程的变化来调整其输出电流，以减少环路带宽的变化。

5. 发明授权

US07362187B1 Sequential VCO phase output enabling circuit 有权
标题翻译：顺序VCO相位输出使能电路
公开(公告)号：US07362187B1
公开(公告)日：2008-04-22
申请号：US11259156
申请日：2005-10-25
申请人： Kang-Wei Lai , Greg Starr
发明人： Kang-Wei Lai , Greg Starr
IPC分类号： H03B27/00
CPC分类号： H03L7/0996 , H03K3/0322 , H03K5/135 , H03K5/15013 , H04L7/033
摘要： Circuits, methods, and apparatus that provide a sequential start-up of outputs of an oscillator following a power-up or restart. The outputs are gated by enable signals. These enable signals are derived sequentially, the first in a series being triggered by a specific output of the oscillator.
摘要翻译：在上电或重新启动后提供振荡器输出的顺序启动的电路，方法和装置。输出由使能信号选通。这些使能信号依次导出，串联中的第一个由振荡器的特定输出触发。

6. 发明授权

US07286007B1 Configurable clock network for programmable logic device 有权
标题翻译：可编程逻辑器件的可配置时钟网络
公开(公告)号：US07286007B1
公开(公告)日：2007-10-23
申请号：US11282876
申请日：2005-11-17
申请人： Gregory Starr , Kang Wei Lai , Richard Y Chang
发明人： Gregory Starr , Kang Wei Lai , Richard Y Chang
IPC分类号： H01L25/00
CPC分类号： H03K19/017581 , G06F1/10
摘要： In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.
摘要翻译：在具有高速串行接口通道的可编程逻辑器件中，用于向这些高速串行接口的动态相位对准电路提供一个或多个高速时钟的时钟分配网络包括至少一个可分段的总线（例如使用可调缓冲区）。这允许总线在高速串行接口以不同的速度运行时被分成不同的部分，可以连接到不同的时钟源。在一个实施例中，分段元件（例如，上述缓冲器）位于所选择的通道（例如，每第四通道）之间，限制不同段的大小。在另一个实施例中，分段元件位于每个通道之间，允许完全用户在选择段的大小时的自由度。因此，代替为每个时钟源提供总线，通过分割单个总线，可以使多个时钟可用于不同的通道。

7. 发明授权

US07276943B2 Highly configurable PLL architecture for programmable logic 有权
标题翻译：用于可编程逻辑的高度可配置的PLL架构
公开(公告)号：US07276943B2
公开(公告)日：2007-10-02
申请号：US11486565
申请日：2006-07-13
申请人： Gregory W. Starr , Wanli Chang , Kang Wei Lai , Mian Z. Smith , Richard Chang
发明人： Gregory W. Starr , Wanli Chang , Kang Wei Lai , Mian Z. Smith , Richard Chang
IPC分类号： H03L7/06
CPC分类号： H03L7/18 , H03L7/081 , H03L7/0996
摘要： A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.
摘要翻译：可编程逻辑器件包括可配置的锁相环（PLL）电路，其输出具有可编程相位和频率的多个时钟信号。每个输出信号可编程选择用作外部时钟，内部全局时钟，内部本地时钟或其组合。 PLL电路具有可编程分频，包括可编程级联分频，以及提供高度时钟设计灵活性的可编程输出信号复用。

8. 发明授权

US08253484B1 Configurable clock network for programmable logic device 有权
标题翻译：可编程逻辑器件的可配置时钟网络
公开(公告)号：US08253484B1
公开(公告)日：2012-08-28
申请号：US13283841
申请日：2011-10-28
申请人： Gregory Starr , Kang Wei Lai , Richard Y. Chang
发明人： Gregory Starr , Kang Wei Lai , Richard Y. Chang
IPC分类号： H01L25/00
CPC分类号： H03K19/017581 , G06F1/10
摘要： In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.
摘要翻译：在具有高速串行接口通道的可编程逻辑器件中，用于向这些高速串行接口的动态相位对准电路提供一个或多个高速时钟的时钟分配网络包括至少一个可分段的总线（例如使用可调缓冲区）。这允许总线在高速串行接口以不同的速度运行时被分成不同的部分，可以连接到不同的时钟源。在一个实施例中，分段元件（例如，上述缓冲器）位于所选择的通道（例如，每第四通道）之间，限制不同段的大小。在另一个实施例中，分段元件位于每个通道之间，允许完全的用户在选择段的尺寸时的自由度。因此，代替为每个时钟源提供总线，通过分割单个总线，可以使多个时钟可用于不同的通道。

9. 发明授权

US07859329B1 Configurable clock network for programmable logic device 有权
标题翻译：可编程逻辑器件的可配置时钟网络
公开(公告)号：US07859329B1
公开(公告)日：2010-12-28
申请号：US12625718
申请日：2009-11-25
申请人： Gregory Starr , Kang Wei Lai , Richard Y. Chang
发明人： Gregory Starr , Kang Wei Lai , Richard Y. Chang
IPC分类号： H01L25/00
CPC分类号： H03K19/017581 , G06F1/10
摘要： In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.
摘要翻译：在具有高速串行接口通道的可编程逻辑器件中，用于向这些高速串行接口的动态相位对准电路提供一个或多个高速时钟的时钟分配网络包括至少一个可分段的总线（例如使用可调缓冲区）。这允许总线在高速串行接口以不同的速度运行时被分成不同的部分，可以连接到不同的时钟源。在一个实施例中，分段元件（例如，上述缓冲器）位于所选择的通道（例如，每第四通道）之间，限制不同段的大小。在另一个实施例中，分段元件位于每个通道之间，允许完全用户在选择段的大小时的自由度。因此，代替为每个时钟源提供总线，通过分割单个总线，可以使多个时钟可用于不同的通道。

10. 发明授权

US07098707B2 Highly configurable PLL architecture for programmable logic 有权
标题翻译：用于可编程逻辑的高度可配置的PLL架构
公开(公告)号：US07098707B2
公开(公告)日：2006-08-29
申请号：US10797836
申请日：2004-03-09
申请人： Gregory W. Starr , Wanli Chang , Kang Wei Lai , Mian Z. Smith , Richard Chang
发明人： Gregory W. Starr , Wanli Chang , Kang Wei Lai , Mian Z. Smith , Richard Chang
IPC分类号： H03L7/06
CPC分类号： H03L7/18 , H03L7/081 , H03L7/0996
摘要： A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.
摘要翻译：可编程逻辑器件包括可配置的锁相环（PLL）电路，其输出具有可编程相位和频率的多个时钟信号。每个输出信号可编程选择用作外部时钟，内部全局时钟，内部本地时钟或其组合。 PLL电路具有可编程分频，包括可编程级联分频，以及提供高度时钟设计灵活性的可编程输出信号复用。

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