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1. 发明授权

US07075365B1 Configurable clock network for programmable logic device 失效
公开(公告)号：US07075365B1
公开(公告)日：2006-07-11
申请号：US10830562
申请日：2004-04-22
申请人： Gregory Starr , Kang Wei Lai , Richard Y. Chang
发明人： Gregory Starr , Kang Wei Lai , Richard Y. Chang
IPC分类号： H01L25/00
CPC分类号： H03K19/017581 , G06F1/10
摘要： In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.

2. 发明授权

US07646237B1 Configurable clock network for programmable logic device 失效
公开(公告)号：US07646237B1
公开(公告)日：2010-01-12
申请号：US11888336
申请日：2007-07-30
申请人： Gregory Starr , Kang Wei Lai , Richard Y Chang
发明人： Gregory Starr , Kang Wei Lai , Richard Y Chang
IPC分类号： H01L25/00
CPC分类号： H03K19/017581 , G06F1/10
摘要： In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.

3. 发明授权

US08253484B1 Configurable clock network for programmable logic device 有权
标题翻译：可编程逻辑器件的可配置时钟网络
公开(公告)号：US08253484B1
公开(公告)日：2012-08-28
申请号：US13283841
申请日：2011-10-28
申请人： Gregory Starr , Kang Wei Lai , Richard Y. Chang
发明人： Gregory Starr , Kang Wei Lai , Richard Y. Chang
IPC分类号： H01L25/00
CPC分类号： H03K19/017581 , G06F1/10
摘要： In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.
摘要翻译：在具有高速串行接口通道的可编程逻辑器件中，用于向这些高速串行接口的动态相位对准电路提供一个或多个高速时钟的时钟分配网络包括至少一个可分段的总线（例如使用可调缓冲区）。这允许总线在高速串行接口以不同的速度运行时被分成不同的部分，可以连接到不同的时钟源。在一个实施例中，分段元件（例如，上述缓冲器）位于所选择的通道（例如，每第四通道）之间，限制不同段的大小。在另一个实施例中，分段元件位于每个通道之间，允许完全的用户在选择段的尺寸时的自由度。因此，代替为每个时钟源提供总线，通过分割单个总线，可以使多个时钟可用于不同的通道。

4. 发明授权

US07859329B1 Configurable clock network for programmable logic device 有权
标题翻译：可编程逻辑器件的可配置时钟网络
公开(公告)号：US07859329B1
公开(公告)日：2010-12-28
申请号：US12625718
申请日：2009-11-25
申请人： Gregory Starr , Kang Wei Lai , Richard Y. Chang
发明人： Gregory Starr , Kang Wei Lai , Richard Y. Chang
IPC分类号： H01L25/00
CPC分类号： H03K19/017581 , G06F1/10
摘要： In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.
摘要翻译：在具有高速串行接口通道的可编程逻辑器件中，用于向这些高速串行接口的动态相位对准电路提供一个或多个高速时钟的时钟分配网络包括至少一个可分段的总线（例如使用可调缓冲区）。这允许总线在高速串行接口以不同的速度运行时被分成不同的部分，可以连接到不同的时钟源。在一个实施例中，分段元件（例如，上述缓冲器）位于所选择的通道（例如，每第四通道）之间，限制不同段的大小。在另一个实施例中，分段元件位于每个通道之间，允许完全用户在选择段的大小时的自由度。因此，代替为每个时钟源提供总线，通过分割单个总线，可以使多个时钟可用于不同的通道。

5. 发明授权

US08441314B1 Configurable clock network for programmable logic device 有权
标题翻译：可编程逻辑器件的可配置时钟网络
公开(公告)号：US08441314B1
公开(公告)日：2013-05-14
申请号：US13558904
申请日：2012-07-26
申请人： Gregory Starr , Kang Wei Lai , Richard Y. Chang
发明人： Gregory Starr , Kang Wei Lai , Richard Y. Chang
IPC分类号： H01L25/00
CPC分类号： H03K19/017581 , G06F1/10
摘要： In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.
摘要翻译：在具有高速串行接口通道的可编程逻辑器件中，用于向这些高速串行接口的动态相位对准电路提供一个或多个高速时钟的时钟分配网络包括至少一个可分段的总线（例如使用可调缓冲区）。这允许总线在高速串行接口以不同的速度运行时被分成不同的部分，可以连接到不同的时钟源。在一个实施例中，分段元件（例如，上述缓冲器）位于所选择的通道（例如，每第四通道）之间，限制不同段的大小。在另一个实施例中，分段元件位于每个通道之间，允许完全用户在选择段的大小时的自由度。因此，代替为每个时钟源提供总线，通过分割单个总线，可以使多个时钟可用于不同的通道。

6. 发明授权

US08072260B1 Configurable clock network for programmable logic device 有权
标题翻译：可编程逻辑器件的可配置时钟网络
公开(公告)号：US08072260B1
公开(公告)日：2011-12-06
申请号：US12951486
申请日：2010-11-22
申请人： Gregory Starr , Kang Wei Lai , Richard Y. Chang
发明人： Gregory Starr , Kang Wei Lai , Richard Y. Chang
IPC分类号： H01L25/00
CPC分类号： H03K19/017581 , G06F1/10
摘要： In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.
摘要翻译：在具有高速串行接口通道的可编程逻辑器件中，用于向这些高速串行接口的动态相位对准电路提供一个或多个高速时钟的时钟分配网络包括至少一个可分段的总线（例如使用可调缓冲区）。这允许总线在高速串行接口以不同的速度运行时被分成不同的部分，可以连接到不同的时钟源。在一个实施例中，分段元件（例如，上述缓冲器）位于所选择的通道（例如，每第四通道）之间，限制不同段的大小。在另一个实施例中，分段元件位于每个通道之间，允许完全用户在选择段的大小时的自由度。因此，代替为每个时钟源提供总线，通过分割单个总线，可以使多个时钟可用于不同的通道。

7. 发明授权

US07286007B1 Configurable clock network for programmable logic device 有权
标题翻译：可编程逻辑器件的可配置时钟网络
公开(公告)号：US07286007B1
公开(公告)日：2007-10-23
申请号：US11282876
申请日：2005-11-17
申请人： Gregory Starr , Kang Wei Lai , Richard Y Chang
发明人： Gregory Starr , Kang Wei Lai , Richard Y Chang
IPC分类号： H01L25/00
CPC分类号： H03K19/017581 , G06F1/10
摘要： In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.
摘要翻译：在具有高速串行接口通道的可编程逻辑器件中，用于向这些高速串行接口的动态相位对准电路提供一个或多个高速时钟的时钟分配网络包括至少一个可分段的总线（例如使用可调缓冲区）。这允许总线在高速串行接口以不同的速度运行时被分成不同的部分，可以连接到不同的时钟源。在一个实施例中，分段元件（例如，上述缓冲器）位于所选择的通道（例如，每第四通道）之间，限制不同段的大小。在另一个实施例中，分段元件位于每个通道之间，允许完全用户在选择段的大小时的自由度。因此，代替为每个时钟源提供总线，通过分割单个总线，可以使多个时钟可用于不同的通道。

8. 发明授权

US07098707B2 Highly configurable PLL architecture for programmable logic 有权
标题翻译：用于可编程逻辑的高度可配置的PLL架构
公开(公告)号：US07098707B2
公开(公告)日：2006-08-29
申请号：US10797836
申请日：2004-03-09
申请人： Gregory W. Starr , Wanli Chang , Kang Wei Lai , Mian Z. Smith , Richard Chang
发明人： Gregory W. Starr , Wanli Chang , Kang Wei Lai , Mian Z. Smith , Richard Chang
IPC分类号： H03L7/06
CPC分类号： H03L7/18 , H03L7/081 , H03L7/0996
摘要： A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.
摘要翻译：可编程逻辑器件包括可配置的锁相环（PLL）电路，其输出具有可编程相位和频率的多个时钟信号。每个输出信号可编程选择用作外部时钟，内部全局时钟，内部本地时钟或其组合。 PLL电路具有可编程分频，包括可编程级联分频，以及提供高度时钟设计灵活性的可编程输出信号复用。

9. 发明授权

US06803803B1 Method and apparatus for compensating circuits for variations in temperature supply and process 有权
标题翻译：用于补偿温度供应和过程变化的电路的方法和装置
公开(公告)号：US06803803B1
公开(公告)日：2004-10-12
申请号：US10206415
申请日：2002-07-26
申请人： Greg Starr , Kang Wei Lai
发明人： Greg Starr , Kang Wei Lai
IPC分类号： H03K1714
CPC分类号： H03K19/00384
摘要： An exemplary compensation circuit includes: a temperature compensation circuit which provides as an output a temperature compensation signal indicative of temperature variations; a supply compensation circuit which provides as an output a supply compensation signal indicative of supply voltage variations; and a compensation conversion circuit coupled to the temperature compensation circuit and the supply compensation circuit to provide as an output a bias signal from the temperature compensation signal and the supply compensation signal. The supply compensation circuit includes a voltage divider circuit coupled to a supply compensation node, to a source voltage, and to a sink voltage, where the supply compensation node is coupled to an input of the compensation conversion circuit. The source voltage provides a supply voltage, and the supply compensation signal is indicative of variations in the supply voltage.
摘要翻译：示例性补偿电路包括：温度补偿电路，其提供表示温度变化的温度补偿信号作为输出; 电源补偿电路，其提供指示电源电压变化的电源补偿信号作为输出; 以及补偿转换电路，耦合到温度补偿电路和电源补偿电路，以提供来自温度补偿信号和电源补偿信号的偏置信号作为输出。电源补偿电路包括耦合到电源补偿节点的分压器电路，源极电压和灌电压，其中电源补偿节点耦合到补偿转换电路的输入。源电压提供电源电压，电源补偿信号表示电源电压的变化。

10. 发明授权

US07276943B2 Highly configurable PLL architecture for programmable logic 有权
标题翻译：用于可编程逻辑的高度可配置的PLL架构
公开(公告)号：US07276943B2
公开(公告)日：2007-10-02
申请号：US11486565
申请日：2006-07-13
申请人： Gregory W. Starr , Wanli Chang , Kang Wei Lai , Mian Z. Smith , Richard Chang
发明人： Gregory W. Starr , Wanli Chang , Kang Wei Lai , Mian Z. Smith , Richard Chang
IPC分类号： H03L7/06
CPC分类号： H03L7/18 , H03L7/081 , H03L7/0996
摘要： A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.
摘要翻译：可编程逻辑器件包括可配置的锁相环（PLL）电路，其输出具有可编程相位和频率的多个时钟信号。每个输出信号可编程选择用作外部时钟，内部全局时钟，内部本地时钟或其组合。 PLL电路具有可编程分频，包括可编程级联分频，以及提供高度时钟设计灵活性的可编程输出信号复用。

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