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1. 发明授权

US09360520B2 Test mode control circuit of semiconductor apparatus and control method thereof 有权
标题翻译：半导体装置的测试模式控制电路及其控制方法
公开(公告)号：US09360520B2
公开(公告)日：2016-06-07
申请号：US13181921
申请日：2011-07-13
申请人： Tae Sik Yun , Jong Chern Lee
发明人： Tae Sik Yun , Jong Chern Lee
IPC分类号： H03K19/00 , G01R31/317 , G11C29/14 , G11C29/46 , G11C29/00
CPC分类号： G01R31/31724 , G11C29/14 , G11C29/46 , G11C29/78 , G11C29/802
摘要： Various embodiments of a test mode control circuit of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, the test mode control circuit may include: a test mode control block configured to generate a plurality of control signal sets in response to a first address signal set and a second address signal set which are sequentially inputted; a test mode transfer block configured to transfer a plurality of test mode signals, which are generated according to a combination of the plurality of control signal sets, to a plurality of circuit blocks of the semiconductor apparatus; and a plurality of global lines configured to transmit the plurality of control signal sets to the test mode transfer block.
摘要翻译：公开了半导体装置的测试模式控制电路的各种实施例及相关方法。在一个示例性实施例中，测试模式控制电路可以包括：测试模式控制块，被配置为响应于顺序地输入的第一地址信号组和第二地址信号组而产生多个控制信号集; 测试模式传送块，被配置为将根据所述多个控制信号组的组合产生的多个测试模式信号传送到所述半导体装置的多个电路块; 以及配置成将多个控制信号组发送到测试模式传送块的多个全局线。

2. 发明授权

US08981841B2 Semiconductor integrated circuit and semiconductor system including the same 有权
标题翻译：半导体集成电路和半导体系统包括相同
公开(公告)号：US08981841B2
公开(公告)日：2015-03-17
申请号：US13236970
申请日：2011-09-20
申请人： Jae-Bum Ko , Jong-Chern Lee , Sang-Jin Byeon
发明人： Jae-Bum Ko , Jong-Chern Lee , Sang-Jin Byeon
IPC分类号： H01L25/00 , G11C8/12
CPC分类号： G11C8/12
摘要： A semiconductor integrated circuit includes a plurality of semiconductor chips respectively selected in response to a plurality of chip selection signals, and a chip selection signal generator configured to generate the chip selection signals in response to one first control signal for deciding whether to drive the semiconductor chips and at least one second control signal for selecting at least one semiconductor chip from among the semiconductor chips.
摘要翻译：半导体集成电路包括分别响应于多个芯片选择信号选择的多个半导体芯片，以及芯片选择信号发生器，被配置为响应于用于决定是否驱动半导体芯片的一个第一控制信号产生芯片选择信号以及用于从半导体芯片中选择至少一个半导体芯片的至少一个第二控制信号。

3. 发明授权

US08547764B2 Semiconductor memory device and method for performing data compression test of the same 失效
标题翻译：半导体存储器件及其执行数据压缩测试的方法
公开(公告)号：US08547764B2
公开(公告)日：2013-10-01
申请号：US12647196
申请日：2009-12-24
申请人： Jae-Woong Yun , Jong-Chern Lee , Hee-Jin Byun
发明人： Jae-Woong Yun , Jong-Chern Lee , Hee-Jin Byun
IPC分类号： G11C7/00
CPC分类号： G11C29/40 , G11C2029/2602
摘要： A semiconductor memory device includes a plurality of data transmission lines, a plurality of parallel-to-serial conversion sections configured to receive, serially align, and output data from at least two of the plurality of data transmission lines, a plurality of data compression circuits configured to receive, compress, and output outputs of at least two of the plurality of parallel-to-serial conversion sections, and a plurality of data output circuits configured to output respective compression results of the plurality of data compression circuits to an outside of a chip.
摘要翻译：半导体存储器件包括多个数据传输线，多个并行到串行转换部分，被配置为从所述多个数据传输线中的至少两个数据传输线接收串行对准和输出数据;多个数据压缩电路被配置为接收，压缩和输出多个并行到串行转换部分中的至少两个的输出，以及多个数据输出电路，被配置为将多个数据压缩电路的各个压缩结果输出到芯片。

4. 发明授权

US08487431B2 Semiconductor integrated circuit having a multi-chip structure 有权
标题翻译：具有多芯片结构的半导体集成电路
公开(公告)号：US08487431B2
公开(公告)日：2013-07-16
申请号：US12833436
申请日：2010-07-09
申请人： Sin-Hyun Jin , Jong-Chern Lee
发明人： Sin-Hyun Jin , Jong-Chern Lee
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06541
摘要： A semiconductor integrated circuit having a multi-chip structure includes a plurality of stacked semiconductor chips. At least one of the semiconductor chips includes first and second metal layers separately formed inside the semiconductor chip, a first internal circuit coupled in series between the first and second metal layers inside the semiconductor chip, a first metal path vertically formed over the second metal layer to a first side of the semiconductor chip, and a first through silicon via formed through the semiconductor chip from a second side of the semiconductor chip to the first metal layer.
摘要翻译：具有多芯片结构的半导体集成电路包括多个层叠的半导体芯片。半导体芯片中的至少一个包括分开形成在半导体芯片内部的第一和第二金属层，串联耦合在半导体芯片内的第一和第二金属层之间的第一内部电路，垂直形成在第二金属层上的第一金属路径到半导体芯片的第一侧，以及通过半导体芯片从半导体芯片的第二侧形成到第一金属层的第一贯穿硅通孔。

5. 发明授权

US08411512B2 Semiconductor memory apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US08411512B2
公开(公告)日：2013-04-02
申请号：US12948936
申请日：2010-11-18
申请人： Chul Kim , Jong Chern Lee
发明人： Chul Kim , Jong Chern Lee
IPC分类号： G11C7/10 , G11C7/22
CPC分类号： G11C7/18 , G11C2207/002
摘要： A semiconductor memory apparatus includes: a memory cell array including a plurality of memory cells; a bit line sense amplifier (BLSA) coupled to the memory cells in the memory cell array through a bit line; a plurality of local input/output lines coupled to the BLSA; and a switching unit coupled to the local input/output lines and configured to select a part of the local input/output lines.
摘要翻译：半导体存储装置包括：包括多个存储单元的存储单元阵列; 通过位线耦合到存储单元阵列中的存储单元的位线读出放大器（BLSA）; 耦合到所述BLSA的多个本地输入/输出线; 以及耦合到本地输入/输出线并被配置为选择本地输入/输出线的一部分的开关单元。

6. 发明申请

US20130009285A1 SEMICONDUCTOR CHIP AND SEMICONDUCTOR WAFER 有权
标题翻译：半导体芯片和半导体晶片
公开(公告)号：US20130009285A1
公开(公告)日：2013-01-10
申请号：US13620404
申请日：2012-09-14
申请人： Jun-Gi Choi , Jong-Chern Lee
发明人： Jun-Gi Choi , Jong-Chern Lee
IPC分类号： H01L23/544
CPC分类号： H01L22/32 , H01L22/34 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer includes at least one chip formed on a substrate, and a scribe line region surrounding the chip. The chip includes a device formation region, and a chip boundary region surrounding the device formation region and formed between the device formation region and the scribe line region. The chip boundary region includes a guard ring structure which physically separates the device formation region from the scribe line region. The guard ring structure includes a signal transfer element which transfers an electric signal between the device formation region and the scribe line region.
摘要翻译：半导体晶片包括形成在基板上的至少一个芯片和围绕芯片的划线区域。芯片包括器件形成区域和围绕器件形成区域并形成在器件形成区域和划线区域之间的芯片边界区域。芯片边界区域包括将器件形成区域与划线区域物理分离的保护环结构。保护环结构包括在器件形成区域和划线区域之间传送电信号的信号传输元件。

7. 发明授权

US08243485B2 Semiconductor apparatus and chip selection method thereof 有权
标题翻译：半导体装置及其芯片选择方法
公开(公告)号：US08243485B2
公开(公告)日：2012-08-14
申请号：US12650501
申请日：2009-12-30
申请人： Sin Hyun Jin , Jong Chern Lee
发明人： Sin Hyun Jin , Jong Chern Lee
IPC分类号： G11C5/02
CPC分类号： H01L24/49 , G11C5/04 , H01L24/48 , H01L25/0657 , H01L2224/48091 , H01L2224/49113 , H01L2225/06513 , H01L2225/06541 , H01L2225/06562 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2224/45099 , H01L2224/05599
摘要： A semiconductor apparatus having a plurality of stacked chips includes: a plurality of latch units, each of which is disposed in a corresponding one of the plurality of chips and is configured to latch a clock signal and a frequency-divided signal at mutually different points of time to generate an chip identification signal of the corresponding one of the plurality of chips; and a plurality of chip selection signal generating units, each of which is disposed in the corresponding one of the plurality of chips and is configured to compare the chip identification signal of the corresponding one of the plurality of chips with a chip selection identification signal to generate a chip selection signal of the corresponding one of the plurality of chips, wherein the chip selection signal is configured to enable the corresponding one of the plurality of chips when the chip identification signal matches the chip selection identification signal.
摘要翻译：具有多个堆叠芯片的半导体装置包括：多个锁存单元，每个锁存单元布置在所述多个芯片中的相应一个芯片中，并且被配置为在时钟信号和分频信号的相互不同的点处锁存时钟信号和分频信号时间来生成多个芯片中的相应一个芯片的芯片识别信号; 以及多个芯片选择信号生成单元，其各自设置在所述多个芯片的对应的一个芯片中，并且被配置为将所述多个芯片中的相应一个芯片的芯片识别信号与芯片选择识别信号进行比较，以生成所述芯片选择信号被配置为当所述芯片识别信号与所述芯片选择识别信号匹配时，使所述多个芯片中的相应一个芯片能够使能。

8. 发明申请

US20120194243A1 SEMICONDUCTOR APPARATUS AND REPAIR METHOD THEREOF 有权
标题翻译：半导体装置及其修理方法
公开(公告)号：US20120194243A1
公开(公告)日：2012-08-02
申请号：US13168241
申请日：2011-06-24
申请人： Min Seok CHOI , Jong Chern LEE
发明人： Min Seok CHOI , Jong Chern LEE
IPC分类号： H03L7/00
CPC分类号： G11C29/025 , G11C29/802 , G11C2029/4402
摘要： A semiconductor apparatus includes a signal transmission block and signal reception blocks. The signal transmission block is disposed in a first chip and configured to transmit fuse information in synchronization with transmission control signals. The signal reception blocks are respectively disposed in the first chip and a second chip and configured to receive the fuse information in synchronization with reception control signals.
摘要翻译：半导体装置包括信号传输块和信号接收块。信号传输块设置在第一芯片中并且被配置为与传输控制信号同步地发送熔丝信息。信号接收块分别设置在第一芯片和第二芯片中，并被配置为与接收控制信号同步地接收熔丝信息。

9. 发明申请

US20120176849A1 SEMICONDUCTOR APPARATUS AND MEMORY SYSTEM INCLUDING THE SAME 有权
标题翻译：半导体器件和包括其的存储器系统
公开(公告)号：US20120176849A1
公开(公告)日：2012-07-12
申请号：US13181956
申请日：2011-07-13
申请人： Jae Bum KO , Jong Chern Lee
发明人： Jae Bum KO , Jong Chern Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/1063 , G11C5/14 , G11C7/1084 , G11C7/109 , G11C8/12
摘要： A semiconductor memory apparatus includes one or more semiconductor chips configured to have predetermined capacity and structure; and a signal level control unit configured to control levels of external signals, which are input to the one or more semiconductor chips, in order to realize various capacities and structures using the one or more semiconductor chips.
摘要翻译：一种半导体存储装置，其具备：具有规定容量和结构的一个以上的半导体芯片; 以及信号电平控制单元，被配置为控制输入到所述一个或多个半导体芯片的外部信号的电平，以便实现使用所述一个或多个半导体芯片的各种容量和结构。

10. 发明申请

US20120154006A1 DUTY CYCLE CORRECTION CIRCUIT 有权
标题翻译：占空比校正电路
公开(公告)号：US20120154006A1
公开(公告)日：2012-06-21
申请号：US13048185
申请日：2011-03-15
申请人： Seung-Joon AHN , Jong-Chern Lee
发明人： Seung-Joon AHN , Jong-Chern Lee
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit includes a duty cycle control unit configured to generate a corrected clock signal by correcting a duty cycle of an input clock signal in response to a control signal, a duty cycle detection unit configured to detect a duty cycle of the corrected clock signal and output a detection signal, and a control signal generation unit configured to generate the control signal in response to the detection signal.
摘要翻译：占空比校正电路包括占空比控制单元，其被配置为通过响应于控制信号校正输入时钟信号的占空比来产生校正时钟信号;占空比检测单元，被配置为检测校正时钟的占空比信号并输出检测信号，以及控制信号生成单元，被配置为响应于检测信号而产生控制信号。

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