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1. 发明授权

US5764714A Latching inputs and enabling outputs on bidirectional pins with a phase locked loop (PLL) lock detect circuit 失效
标题翻译：使用锁相环（PLL）锁定检测电路在双向引脚上锁存输入和使能输出
公开(公告)号：US5764714A
公开(公告)日：1998-06-09
申请号：US700249
申请日：1996-08-20
申请人： Galen E. Stansell , J. Kenneth Fox , Eric N. Mann , James P. Myers , Timothy V. Wright
发明人： Galen E. Stansell , J. Kenneth Fox , Eric N. Mann , James P. Myers , Timothy V. Wright
IPC分类号： H03L7/07 , H03L7/089 , H03L7/095 , G06F13/00
CPC分类号： H03L7/095 , H03L7/07 , H03L7/089 , Y10S331/02
摘要： A circuit for latching inputs and enabling outputs on a bidirectional pin using a PLL lock detect circuit is disclosed. A PLL lock detect circuit generates an active lock control signal when an output reference signal is phase locked relative to an input reference signal applied to a phase locked loop (PLL) circuit. A latch and enable circuit is responsive to this lock control signal to latch the input signal (off of the pin), and, thereafter, enable output of an output signal onto the bidirectional pin. The latch and enable circuit includes a data latch to store the input signal when the lock control signal goes to an active state. The latch and enable circuit also includes a delay circuit to delay the lock control signal to produce a delayed lock control signal, and a tristateable output driver that is tristated when the delayed lock control signal is inactive, but, operates to pass (i.e., enable) the output signal to the bidirectional pin when the delayed lock control signal is active.
摘要翻译：公开了一种用于使用PLL锁定检测电路锁存输入和使能双向引脚的输出的电路。当输出参考信号相对于施加到锁相环（PLL）电路的输入参考信号相位锁定时，PLL锁定检测电路产生有效锁定控制信号。锁存器和使能电路响应于该锁定控制信号来锁存输入信号（引脚之外），然后使输出信号输出到双向引脚上。当锁定控制信号进入活动状态时，锁存器和使能电路包括数据锁存器以存储输入信号。锁存器和使能电路还包括延迟电路以延迟锁定控制信号以产生延迟的锁定控制信号，以及当延迟的锁定控制信号无效但被操作以通过时（即，使能）的三态输出驱动器）当延迟锁定控制信号有效时，输出信号到双向引脚。

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