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1. 发明授权

US08869126B2 Method and apparatus enabling multi threaded program execution for a Cobol program including OpenMP directives by utilizing a two-stage compilation process 有权
标题翻译：通过利用两阶段编译过程，可以实现包括OpenMP指令在内的Cobol程序的多线程程序执行的方法和装置
公开(公告)号：US08869126B2
公开(公告)日：2014-10-21
申请号：US13729490
申请日：2012-12-28
申请人： Cynthia S. Guenthner , Russell W. Guenthner , John Edward Heath , Albert Henry John Wigchert , F. Michel Brown , Nicholas John Colasacco , Clinton B. Eckard
发明人： Cynthia S. Guenthner , Russell W. Guenthner , John Edward Heath , Albert Henry John Wigchert , F. Michel Brown , Nicholas John Colasacco , Clinton B. Eckard
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： A method and apparatus is disclosed for compilation of an original Cobol program with support for improved performance by increased parallelism during execution using multiple threads of processing. The approach includes a two stage compilation process, the first compilation/translation step by a first specialized compiler/translator that takes as input a Cobol source program that includes parallelization directives, and produces as output an intermediate computer program in a second computer programming language, the intermediate program including parallelization directives in the second computer programming language. The intermediate program is then compiled utilizing a selected second compiler that provides support for parallelism described in the second programming language. The approach optionally allows for use of pragmas serving as parallelization directives to the compiler in the original Cobol program or in the intermediate program.
摘要翻译：公开了一种用于编译原始Cobol程序的方法和装置，其支持通过使用多个处理线程在执行期间通过增加的并行性来提高性能。该方法包括两阶段编译过程，第一个专业编译器/翻译器的第一个编译/翻译步骤，将包含并行化指令的Cobol源程序作为输入，并以第二计算机编程语言生成中间计算机程序作为输出，中间程序包括第二计算机编程语言中的并行化指令。然后使用提供对第二编程语言中描述的并行性的支持的所选择的第二编译器来编译中间程序。该方法可以允许在原始Cobol程序或中间程序中使用用作并行指令的编译指示给编译器。

2. 发明授权

US08856759B2 Method and apparatus providing COBOL decimal type arithmetic functions with improved performance 有权
标题翻译：提供具有改进性能的COBOL十进制算术函数的方法和装置
公开(公告)号：US08856759B2
公开(公告)日：2014-10-07
申请号：US12658017
申请日：2010-02-01
申请人： Russell W. Guenthner , Clinton B. Eckard
发明人： Russell W. Guenthner , Clinton B. Eckard
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F8/49 , G06F8/41 , G06F8/4441 , G06F9/4484
摘要： A method and apparatus is disclosed providing an improvement in performance for arithmetic computations by a computer system for calculations which include decimal numeric variables. The improvement in at least one embodiment includes use of a special compiler in cooperation with a special decimal numeric subroutine library. The compiler provides comparative alignment information based upon comparing alignments of a plurality of decimal variables. The decimal subroutine library can then provide improved performance at run time by utilizing the information compared by the compiler at compiler time rather than making those computations repeatedly at run time.
摘要翻译：公开了一种方法和装置，其通过计算机系统提供包括十进制数字变量的计算的算术计算性能的改进。至少一个实施例的改进包括与特殊的十进制数字子程序库协同使用特殊的编译器。编译器基于比较多个十进制变量的比对来提供比较对齐信息。然后，十进制子程序库可以通过利用编译器在编译器时比较的信息在运行时提供改进的性能，而不是在运行时重复进行这些计算。

3. 发明申请

US20110191755A1 Method and apparatus providing COBOL decimal type arithmetic functions with improved performance 有权
标题翻译：提供具有改进性能的COBOL十进制算术函数的方法和装置
公开(公告)号：US20110191755A1
公开(公告)日：2011-08-04
申请号：US12658017
申请日：2010-02-01
申请人： Russell W. Guenthner , Clinton B. Eckard
发明人： Russell W. Guenthner , Clinton B. Eckard
IPC分类号： G06F9/45
CPC分类号： G06F8/49 , G06F8/41 , G06F8/4441 , G06F9/4484
摘要： A method and apparatus is disclosed providing an improvement in performance for arithmetic computations by a computer system for calculations which include decimal numeric variables. The improvement in at least one embodiment includes use of a special compiler in cooperation with a special decimal numeric subroutine library. The compiler provides comparative alignment information based upon comparing alignments of a plurality of decimal variables. The decimal subroutine library can then provide improved performance at run time by utilizing the information compared by the compiler at compiler time rather than making those computations repeatedly at run time.
摘要翻译：公开了一种方法和装置，其通过计算机系统提供包括十进制数字变量的计算的算术计算性能的改进。至少一个实施例的改进包括与特殊的十进制数字子程序库协同使用特殊的编译器。编译器基于比较多个十进制变量的比对来提供比较对齐信息。然后，十进制子程序库可以通过利用编译器在编译器时比较的信息在运行时提供改进的性能，而不是在运行时重复进行这些计算。

4. 发明授权

US07653527B2 Runtime selection of code variants in a multiprogram computer hardware emulation system 有权
标题翻译：多重程序计算机硬件仿真系统中运行时代码变体的选择
公开(公告)号：US07653527B2
公开(公告)日：2010-01-26
申请号：US11323843
申请日：2005-12-29
申请人： Russell W. Guenther , Clinton B. Eckard , David W. Selway
发明人： Russell W. Guenther , Clinton B. Eckard , David W. Selway
IPC分类号： G06F9/455
CPC分类号： G06F9/45537
摘要： As fast and powerful commodity processors have been developed, it has become practical to emulate the proprietary hardware systems of powerful older computers on platforms built using commodity processors. The systems being emulated are often large mainframe computers with large numbers of disks, communications systems and other attached hardware. Because of the size and expense, and also because databases involved must reside in only one location, it is difficult to replicate these systems for testing, development, debug or for providing alternative options to customers. A method for providing a single emulated computer system which provides for multiple views or options in control of the emulator is disclosed in which the options are dependent and selected based on job or user basis. The mechanism continues to provide for high performance and a single copy of the operating system with multiple processes, jobs and threads being emulated under user controlled parameters.
摘要翻译：随着快速且强大的商品处理器的开发，在使用商品处理器构建的平台上模拟强大的旧版计算机的专有硬件系统变得实际可行。正在仿真的系统通常是具有大量磁盘，通信系统和其他附加硬件的大型主机。由于大小和费用，并且因为所涉及的数据库只能驻留在一个位置，所以难以复制这些系统进行测试，开发，调试或为客户提供替代选项。公开了一种提供在仿真器的控制中提供多个视图或选项的单个仿真计算机系统的方法，其中选项依赖于和基于作业或用户的选择。该机制继续提供具有多个进程，作业和线程的操作系统的高性能和单一副本，在用户控制的参数下进行仿真。

5. 发明授权

US6052700A Calendar clock caching in a multiprocessor data processing system 有权
标题翻译：日历时钟缓存在多处理器数据处理系统中
公开(公告)号：US6052700A
公开(公告)日：2000-04-18
申请号：US156104
申请日：1998-09-17
申请人： Clinton B. Eckard , William A. Shelly
发明人： Clinton B. Eckard , William A. Shelly
IPC分类号： G06F1/12 , G06F1/14 , G06F12/08
CPC分类号： G06F11/26 , G06F11/2242 , G06F11/24 , G06F1/14 , G06F12/0833
摘要： Each processor (92) in a data processing system (80) caches a copy of the master calendar clock (97). The master calendar clock (97) and all of the cached calendar clocks (272) are periodically incremented utilizing a common clock (99). Whenever a processor (92) in the system (80) loads the master calendar clock (97) with a new value, that processor (92) broadcasts a cached calendar clock updated interrupt signal (276) to all of the processors in the system. In response to this interrupt (278), each processor (92) clears its cached calendar clock valid flag (274). Whenever a read calendar clock instruction is executed on a processor (92), the flag (274) is tested, and if set, its cached calendar clock (272) value is returned. Otherwise, the master calendar clock (97) value is retrieved, written to that processor's cached calendar clock (272), and returned. The cached calendar clock valid flag (274) is set to indicate a valid cached calendar clock (272).
摘要翻译：数据处理系统（80）中的每个处理器（92）缓存主日历时钟（97）的副本。使用公共时钟（99）来周期性地增加主日历时钟（97）和所有缓存的日历时钟（272）。只要系统（80）中的处理器（92）以新值加载主日历时钟（97），该处理器（92）向系统中的所有处理器广播高速缓存的日历时钟更新的中断信号（276）。响应于该中断（278），每个处理器（92）清除其缓存的日历时钟有效标志（274）。每当在处理器（92）上执行读取日历时钟指令时，测试标志（274），并且如果被设置，则返回其高速缓存的日历时钟（272）值。否则，检索主日历时钟（97）值，写入该处理器的缓存日历时钟（272）并返回。高速缓存的日历时钟有效标志（274）被设置为指示有效的高速缓存日历时钟（272）。

6. 发明授权

US5995992A Conditional truncation indicator control for a decimal numeric processor employing result truncation 失效
标题翻译：采用结果截断的十进制数字处理器的条件截断指示器控制
公开(公告)号：US5995992A
公开(公告)日：1999-11-30
申请号：US971445
申请日：1997-11-17
申请人： Clinton B. Eckard
发明人： Clinton B. Eckard
IPC分类号： G06F9/302 , G06F9/32 , G06F7/38
CPC分类号： G06F9/3001 , G06F9/30094
摘要： In a coprocessor which processes operands and issues a result word which may include overflow, result and truncation fields and which normally sets a truncation indicator if truncation is employed, the setting of the truncation indicator is inhibited under certain conditions to facilitate later handling of the result. Determinations are made as to whether the result and truncation fields of the result word are zero and as to whether the overflow field is non-zero. If the result and truncation fields are zero, the setting of the truncation indicator is inhibited notwithstanding a non-zero value in the overflow field. Break point position information is processed to obtain masks of bits having logic "1" values for testing the result and truncation fields and logic "0" values for testing the overflow field, the masks then being logically ANDed with the result word. If the result of the ANDing process is a logic "0", the truncation indicator is inhibited from being set.
摘要翻译：在处理操作数并发出可能包括溢出，结果和截断字段的结果字的协处理器中，并且如果采用截断通常设置截断指示符，则在某些条件下禁止对截断指示符的设置以便稍后处理结果。确定结果字的结果和截断字段是否为零，以及溢出字段是否为非零。如果结果和截断字段为零，则截断指示符的设置即使在溢出字段中具有非零值也被禁止。处理断点位置信息以获得具有逻辑“1”值的位的掩码，用于测试结果和用于测试溢出字段的截断字段和逻辑“0”值，然后屏蔽与结果字进行逻辑“与”。如果ANDing过程的结果为逻辑“0”，则截断指示器被禁止设置。

7. 发明授权

US5251321A Binary to binary coded decimal and binary coded decimal to binary conversion in a VLSI central processing unit 失效
标题翻译：在VLSI中央处理单元中二进制到二进制编码十进制和二进制编码十进制到二进制转换
公开(公告)号：US5251321A
公开(公告)日：1993-10-05
申请号：US954437
申请日：1992-09-30
申请人： Donald C. Boothroyd , Clinton B. Eckard , Ronald E. Lange , William A. Shelly , Ronald W. Yoder
发明人： Donald C. Boothroyd , Clinton B. Eckard , Ronald E. Lange , William A. Shelly , Ronald W. Yoder
IPC分类号： G06F9/30 , H03M7/12 , G06F5/06
CPC分类号： G06F9/30025 , H03M7/12
摘要： Binary-Coded-Decimal to binary (DTB) and binary to Binary Coded Decimal (BTD) instructions are executed by an address and execution (AX) chip, a decimal numeric (DN) chip, and a cache. For a DTB instruction, the DN chip receives the operand to be converted from the cache, saves the sign, and stores it in a conversion register. When a bit is converted, a Ready-to-Send signal is sent on a COMFROM bus with a Ready-to-Receive Command on a COMTO bus causes the AX chip to accept the bit and the DN chip to generate the next bit until the resultant operand is produced. If the operand to be converted is negative, the DN chip inverts each remaining bit after the first "1" to obtain a two's-complement result. The result in either case is sent to the cache. For a BTD instruction, the AX chip receives the operand to be converted from the cache, send the sign bit to the DN chip and then the bits of the operand when the Ready-to-Send and Ready to Ready-to-Receive signals are produced. The resultant operand is sent to the conversion register. If the operand is negative, all bits are inverted, and a one is added to produce the resultant in two's complement notation.
摘要翻译：二进制编码 - 十进制到二进制（DTB）和二进制到二进制编码十进制（BTD）指令由地址和执行（AX）芯片，十进制数字（DN）芯片和高速缓存执行。对于DTB指令，DN芯片接收要从缓存转换的操作数，保存该符号，并将其存储在转换寄存器中。当一个位被转换时，COMFROM总线上发送一个即时发送信号，COMTO总线上的就绪接收命令使AX芯片接受该位，并且DN芯片产生下一个位，直到产生合成操作数。如果要转换的操作数为负，则DN芯片在第一个“1”之后反转每个剩余的位，以获得二进制补码结果。任一情况下的结果都将发送到缓存。对于BTD指令，AX芯片接收要从高速缓存转换的操作数，将符号位发送到DN芯片，然后在即将发送和就绪准备就绪信号为零时，操作数的位生产。结果操作数被发送到转换寄存器。如果操作数为负，则所有位都被反转，并且添加一个位以产生以二进制补码表示的结果。

8. 发明申请

US20140189664A1 METHOD FOR ENABLING COMPILATION OF A COBOL SOURCE PROGRAM UTILIZING A TWO-STAGE COMPILATION PROCESS, THE COBOL SOURCE PROGRAM INCLUDING A MIX OF COBOL, C++ or JAVA STATEMENTS, AND OPTIONAL OPENMP DIRECTIVES 有权
标题翻译：使用两阶段编译过程的COBOL源程序的编译方法，包括COBOL，C ++或JAVA语句的混合的COBOL源程序和可选的OPENMP指令
公开(公告)号：US20140189664A1
公开(公告)日：2014-07-03
申请号：US13730123
申请日：2012-12-28
申请人： Russell WAYNE Guenthner , Todd Bradley Kneisel , Albert Henry John Wigchert , Clinton B. Eckard
发明人： Russell WAYNE Guenthner , Todd Bradley Kneisel , Albert Henry John Wigchert , Clinton B. Eckard
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： A method, apparatus, and program product are disclosed for carrying out the compilation of an original Cobol program that includes a mix of Cobol, C++ or JAVA and optional OpenMP directives in a single source program file so as to provide improved performance during execution of the program and improved convenience and features in programming. The approach or method includes performing a compilation (or translation) step utilizing a first compiler or translating program which is a is a specialized compiler/translator that takes as input a Cobol source program including a further provision for the inclusion of C/C++ program statements and OpenMP statements, and produces as output an intermediate computer program, the intermediate program that is entirely in C or C++, the intermediate program being intended for further compilation by an existing selected second compiler, the second compiler being an optimizing compiler that provides support for parallelism for the programs described in the C/C++ programming languages.
摘要翻译：公开了一种方法，装置和程序产品，用于在单个源程序文件中执行包括Cobol，C ++或JAVA的组合以及可选的OpenMP指令的原始Cobol程序的编译，以便在执行期间提供改进的性能程序和改进的方便性和编程特性。该方法或方法包括使用第一编译器或翻译程序来执行编译（或翻译）步骤，其是专门的编译器/翻译器，其将Cobol源程序作为输入，Cobol源程序包括用于包含C / C ++程序语句的进一步规定和OpenMP语句，并且产生中间计算机程序，即完全在C或C ++中的中间程序，中间程序用于由现有的选择的第二编译器进一步编译，第二编译器是提供对用于C / C ++编程语言描述的程序的并行性。

9. 发明申请

US20140189663A1 METHOD AND APPARATUS ENABLING MULTI THREADED PROGRAM EXECUTION FOR A COBOL PROGRAM INCLUDING OPENMP DIRECTIVES BY UTILIZING A TWO-STAGE COMPILATION PROCESS 有权
标题翻译：方法和装置通过利用两阶段编译过程实现包括OPENMP指令的COBOL程序的多线程程序执行
公开(公告)号：US20140189663A1
公开(公告)日：2014-07-03
申请号：US13729490
申请日：2012-12-28
申请人： Cynthia S. Guenthner , Russell W. Guenthner , John Edward Heath , Albert Henry John Wigchert , F. Michel Brown , Nicholas John Colasacco , Clinton B. Eckard
发明人： Cynthia S. Guenthner , Russell W. Guenthner , John Edward Heath , Albert Henry John Wigchert , F. Michel Brown , Nicholas John Colasacco , Clinton B. Eckard
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： A method and apparatus is disclosed for compilation of an original Cobol program with support for improved performance by increased parallelism during execution using multiple threads of processing. The approach includes a two stage compilation process, the first compilation/translation step by a first specialized compiler/translator that takes as input a Cobol source program that includes parallelization directives, and produces as output an intermediate computer program in a second computer programming language, the intermediate program including parallelization directives in the second computer programming language. The intermediate program is then compiled utilizing a selected second compiler that provides support for parallelism described in the second programming language. The approach optionally allows for use of pragmas serving as parallelization directives to the compiler in the original Cobol program or in the intermediate program.
摘要翻译：公开了一种用于编译原始Cobol程序的方法和装置，其支持通过使用多个处理线程在执行期间通过增加的并行性来提高性能。该方法包括两阶段编译过程，第一个专业编译器/翻译器的第一个编译/翻译步骤，将包含并行化指令的Cobol源程序作为输入，并以第二计算机编程语言生成中间计算机程序作为输出，中间程序包括第二计算机编程语言中的并行化指令。然后使用提供对第二编程语言中描述的并行性的支持的所选择的第二编译器来编译中间程序。该方法可以允许在原始Cobol程序或中间程序中使用用作并行指令的编译指示给编译器。

10. 发明授权

US07809547B2 Host computer system emulating target system legacy software and providing for incorporating more powerful application program elements into the flow of the legacy software 失效
标题翻译：主机计算机系统模拟目标系统遗留软件，并提供将更强大的应用程序元素并入到传统软件的流程中
公开(公告)号：US07809547B2
公开(公告)日：2010-10-05
申请号：US11324052
申请日：2005-12-29
申请人： Russell W. Guenthner , David W. Selway , Stefan R. Bohult , Clinton B. Eckard
发明人： Russell W. Guenthner , David W. Selway , Stefan R. Bohult , Clinton B. Eckard
IPC分类号： G06F9/455 , G06F9/45 , G06F9/44 , G06F9/00 , G06F9/04
CPC分类号： G06F9/455
摘要： As manufacturers of very fast and powerful commodity processors continue to improve the capabilities of their products, it has become practical to emulate the proprietary hardware and operating systems of powerful older computers on platforms built using commodity processors such that the manufacturers of the older computers can provide new systems which allow their customers to continue to use their highly-regarded proprietary legacy software on state-of-the-art new computer systems by emulating the older computer in software that runs on the new systems. In an example of the subject invention, a 64-bit Cobol Virtual Machine instruction provides the capability of adding to or improving the performance of legacy 36-bit Cobol code. Legacy Cobol instructions can be selectively diverted, in the host CPU, to a 64 bit Virtual Machine Implementation. The output legacy and new Cobol code is compiled in a dedicated implementation of the Cobol compiler, and the output of the special purpose compiler is emulated in a special purpose software emulator, separate from the main software emulator that handles the normal 36-bit stream of legacy code.
摘要翻译：随着非常快速和强大的商品处理器的制造商不断提高其产品的能力，在使用商品处理器构建的平台上模拟强大的旧版计算机的专有硬件和操作系统变得务实，这样老式计算机的制造商可以提供新系统允许他们的客户通过在新系统上运行的软件模拟旧的计算机，继续使用他们备受赞誉的专有遗留软件在最先进的新计算机系统上。在本发明的一个示例中，64位Cobol虚拟机指令提供添加或改善传统36位Cobol代码的性能的能力。传统Cobol指令可以在主机CPU中选择性转移到64位虚拟机实现。输出遗留和新的Cobol代码是在Cobol编译器的专用实现中编译的，专用编译器的输出在专用软件仿真器中仿真，与主软件仿真器分离，处理正常的36位流遗留代码

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