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1. 发明授权

US06324609B1 Method and apparatus providing an improved PCI bus system 失效
标题翻译：提供改进的PCI总线系统的方法和装置
公开(公告)号：US06324609B1
公开(公告)日：2001-11-27
申请号：US09132737
申请日：1998-08-12
申请人： Barry R. Davis , Scott Goble
发明人： Barry R. Davis , Scott Goble
IPC分类号： G06F13368
CPC分类号： G06F13/404 , G06F13/4027
摘要： A PCI-to-PCI bridge having a processor configured for performing various routing mode operations based upon the addresses of transactions carried on interconnected PCI buses. The various routing modes operate on decoded PCI addresses and are known as “programmable decode modes.” In one programmable decode mode, private address spaces are defined for allowing two or more devices interconnected to a secondary PCI bus to communicate directly using private transactions. In another programmable decode mode, subtractive routing operations are provided wherein a secondary PCI interface captures any transactions not claimed on the secondary PCI bus after a predetermined number of clock cycles. Another programmable decode mode is “intelligent” bridging wherein conventional inverse positive decode operations are disabled for the entire primary address space of the secondary PCI bus.
摘要翻译：一种具有处理器的PCI至PCI桥，该处理器被配置为基于在互连PCI总线上承载的事务的地址来执行各种路由模式操作。各种路由模式对解码的PCI地址进行操作，称为“可编程解码模式”。在一个可编程解码模式中，专用地址空间被定义为允许与辅助PCI总线互连的两个或多个设备直接使用私有交易进行通信。在另一个可编程解码模式中，提供了减法路由操作，其中辅助PCI接口在经过预定数量的时钟周期之后捕获在辅助PCI总线上未请求的任何事务。另一个可编程解码模式是“智能”桥接，其中对辅助PCI总线的整个主地址空间禁用常规的反向正解码操作。

2. 发明授权

US06260094B1 Method and apparatus providing programmable decode modes for secondary PCI bus interfaces 有权
标题翻译：为辅助PCI总线接口提供可编程解码模式的方法和装置
公开(公告)号：US06260094B1
公开(公告)日：2001-07-10
申请号：US09133926
申请日：1998-08-13
申请人： Barry R. Davis , Scott Goble
发明人： Barry R. Davis , Scott Goble
IPC分类号： G06F1338
CPC分类号： G06F13/404 , G06F13/4027
摘要： A PCI-to-PCI having programmable decode modes comprising at least one of a standard bridge data transfer transaction, an intelligent bridge data transfer transaction, and a private address space data transfer transaction, and wherein the transactions are configured to bypass a host bus.
摘要翻译：具有可编程解码模式的PCI至PCI包括标准桥接数据传输事务，智能桥数据传输事务和专用地址空间数据传输事务中的至少一个，并且其中所述事务被配置为绕过主机总线。

3. 发明授权

US06460108B1 Low cost data streaming mechanism 有权
标题翻译：低成本数据流传输机制
公开(公告)号：US06460108B1
公开(公告)日：2002-10-01
申请号：US09282386
申请日：1999-03-31
申请人： Jeff J. McCoskey , Richard P. Mackey , Barry R. Davis
发明人： Jeff J. McCoskey , Richard P. Mackey , Barry R. Davis
IPC分类号： G06F1300
CPC分类号： G06F13/4059
摘要： A method and apparatus for providing an efficient, low cost data streaming mechanism from a first bus architecture to a second bus architecture across a bus bridge. Separate read and write data queues are provided in the bus bridge for transfer of data in both directions, and the speed of one of the buses is increased over the speed of the other one of the buses. In one embodiment, the first bus is a PCI bus and the second bus is an internal CPU bus.
摘要翻译：一种用于在总线桥上从第一总线架构向第二总线架构提供有效的低成本数据流机制的方法和装置。在总线桥中提供单独的读写数据队列，用于在两个方向上传输数据，其中一条总线的速度在另一条总线的速度上增加。在一个实施例中，第一总线是PCI总线，第二总线是内部CPU总线。

4. 发明授权

US5857090A Input/output subsystem having an integrated advanced programmable interrupt controller for use in a personal computer 失效
标题翻译：具有用于个人计算机的集成高级可编程中断控制器的输入/输出子系统
公开(公告)号：US5857090A
公开(公告)日：1999-01-05
申请号：US581162
申请日：1995-12-29
申请人： Barry R. Davis , Bruce Young
发明人： Barry R. Davis , Bruce Young
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A computer system is described having one or more host processors, a host chipset and a input/output (I/O) subsystem. The host processors are connected to the host chipset by a host bus. The host chipset is connected to the input/output subsystem by a primary personal computer interface (PCI) bus. The I/O subsystem is connected to I/O devices by a secondary PCI bus. The I/O subsystem includes advanced programmable interrupt controller (APIC) functionality typically provided within an I/O APIC chip within a host chipset. The APIC functionality of the I/O subsystem is primarily implemented in software executing on a core processor of the I/O subsystem. The software creates and accesses various APIC registers and tables, such as a redirection table, within a memory of the I/O subsystem. A single 3-wire APIC bus interconnects the host processors with the I/O subsystem. With this arrangement, non-PCI interrupt lines from the I/O devices are connected only into the I/O subsystem, rather than into the host chipset.
摘要翻译：描述了具有一个或多个主机处理器，主机芯片组和输入/输出（I / O）子系统的计算机系统。主处理器通过主机总线连接到主机芯片组。主机芯片组通过主要个人计算机接口（PCI）总线连接到输入/输出子系统。 I / O子系统通过辅助PCI总线连接到I / O设备。 I / O子系统包括通常在主机芯片组内的I / O APIC芯片内提供的高级可编程中断控制器（APIC）功能。 I / O子系统的APIC功能主要是在I / O子系统的核心处理器上执行的软件中实现的。该软件在I / O子系统的存储器内创建和访问各种APIC寄存器和表，如重定向表。单个3线APIC总线将主机处理器与I / O子系统互连。通过这种安排，来自I / O设备的非PCI中断线仅连接到I / O子系统中，而不是连接到主机芯片组中。

5. 发明授权

US5838935A Method and apparatus providing programmable decode modes for secondary PCI bus interfaces 失效
标题翻译：为辅助PCI总线接口提供可编程解码模式的方法和装置
公开(公告)号：US5838935A
公开(公告)日：1998-11-17
申请号：US580838
申请日：1995-12-29
申请人： Barry R. Davis , Scott Goble
发明人： Barry R. Davis , Scott Goble
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/404 , G06F13/4027
摘要： A PCI-to-PCI bridge is described having a processor configured for performing various routing operations based upon the addresses of transactions carried on interconnected PCI buses. The various routing modes operate on decoded PCI addresses and are described herein as "programmable decode modes." In one programmable decode mode, private address spaces facilitate communication between peer PCI devices without burdening the primary PCI bus or any upstream components such as a host-to-PCI bridge, a host bus and host microprocessors. In another programmable decode mode, subtractive routing operations are provided wherein a secondary PCI interface captures any transactions not claimed on the secondary PCI bus after a predetermined number of clock cycles. The transactions are routed to the primary PCI bus. Another programmable decode mode is "intelligent" bridging wherein conventional inverse positive decode operations are disabled for the entire primary address space of the secondary PCI bus. Only addresses within programmable reverse positive decode address spaces are captured by the secondary PCI interface and forwarded to the corresponding primary PCI bus. Intelligent bridging allows, among other functions, the interconnection of two peer primary PCI buses by a single PCI-to-PCI bridge. Such enables transactions between PCI devices of the peer PCI buses to be routed over the PCI-to-PCI bridge without requiring routing through a host bus.
摘要翻译：描述了具有处理器的PCI至PCI桥，所述处理器被配置为基于在互连的PCI总线上承载的事务的地址来执行各种路由操作。各种路由模式对解码的PCI地址进行操作，并在此被描述为“可编程解码模式”。在一个可编程解码模式中，专用地址空间便于对等PCI设备之间的通信，而不会增加主PCI总线或任何上游组件，例如主机到PCI桥，主机总线和主机微处理器。在另一个可编程解码模式中，提供了减法路由操作，其中辅助PCI接口在经过预定数量的时钟周期之后捕获在辅助PCI总线上未请求的任何事务。事务被路由到主PCI总线。另一个可编程解码模式是“智能”桥接，其中对辅助PCI总线的整个主地址空间禁用常规的反向正解码操作。只有可编程反向正解码地址空间内的地址才被辅助PCI接口捕获并转发到相应的主PCI总线。智能桥接除了其他功能之外还允许通过单个PCI到PCI桥连接两个对等主PCI总线。这样使得对等PCI总线的PCI设备之间的交易能够通过PCI-PCI桥路由而不需要通过主机总线进行路由。

6. 发明授权

US07007126B2 Accessing a primary bus messaging unit from a secondary bus through a PCI bridge 失效
标题翻译：通过PCI桥从辅助总线访问主总线消息单元
公开(公告)号：US07007126B2
公开(公告)日：2006-02-28
申请号：US09023494
申请日：1998-02-13
申请人： Byron R. Gillespie , Barry R. Davis , William Futral
发明人： Byron R. Gillespie , Barry R. Davis , William Futral
IPC分类号： G06F13/38
CPC分类号： G06F13/404 , G06F12/0284
摘要： An I/O subsystem having a processor, a bridge unit, and an I/O messaging unit that couple a primary, secondary and tertiary bus in a computer system. The bridge unit is configurable to claim requests that access a messaging unit (MU) address range from the secondary bus, the MU itself being coupled to the primary bus. The MU interrupts the processor when an I/O request is posted, in response to which the processor reads from the MU pointers to an I/O messages and may then execute the I/O message. To promote the portability of software written for agents on either the primary or the secondary bus that wish to access the MU, the primary and secondary address translation units of the I/O subsystem are programmed to claim the same address translation window, where the MU address range is a portion of the primary ATU address translation window, and the secondary ATU is configured to not claim requests within the MU address range. In a particular embodiment, the I/O subsystem may be implemented as a single integrated circuit chip (I/O processor) which is configured to support the intelligent I/O (I2O®) protocol in connection with Peripheral Components Interconnect (PCI) primary and secondary system busses. By configuring the bridge to claim the MU address range on the secondary bus, the I/O subsystem may permit agents on the secondary bus to perform the I2O protocol without interrupting the host processor which normally resides on the primary PCI bus.
摘要翻译：具有处理器，桥接单元和将计算机系统中的主要，次要和第三总线耦合的I / O消息单元的I / O子系统。桥单元可配置为声明从辅助总线访问消息单元（MU）地址范围的请求，MU本身耦合到主总线。当发出I / O请求时，MU中断处理器，响应处理器从MU指针读取到I / O消息，然后可以执行I / O消息。为了促进在希望访问MU的主总线或辅助总线上为代理编写的软件的可移植性，I / O子系统的主地址转换单元和辅助地址转换单元被编程为要求相同的地址转换窗口，其中MU 地址范围是主ATU地址转换窗口的一部分，并且辅助ATU被配置为不在MU地址范围内要求请求。在特定实施例中，I / O子系统可以被实现为单个集成电路芯片（I / O处理器），其被配置为支持智能I / O（I 2 O）协议与外围组件互连（PCI）主要和次要系统总线相关。通过配置桥接器要求辅助总线上的MU地址范围，I / O子系统可以允许辅助总线上的代理执行I＆lt; 2＆gt; O协议，而不中断通常驻留在主机处理器主PCI总线。

7. 发明授权

US06298407B1 Trigger points for performance optimization in bus-to-bus bridges 失效
标题翻译：总线到总线桥梁性能优化的触发点
公开(公告)号：US06298407B1
公开(公告)日：2001-10-02
申请号：US09034624
申请日：1998-03-04
申请人： Barry R. Davis , Nick G. Eskandari
发明人： Barry R. Davis , Nick G. Eskandari
IPC分类号： G06F1300
CPC分类号： G06F13/4054
摘要： Method and apparatus for tuning the performance of bridge devices, including PCI-to-PCI bridges as well as PCI local bus bridges (or host bridges). The embodiments of the invention permit a multiple-bus computer system to be tuned in view of the application and the bridge queue sizes. Such applications include those concerned with raw bandwidth (such as disk storage), and those that are sensitive to latency (such as networking and videoconferencing). The embodiments of the invention feature a control register that specifies storage conditions to be met by the read and write queues of the bridge. The programmed storage conditions are trigger points which cause the bridge to transfer data into or remove data from the queues during read and write transactions in order to promote the performance (throughput or latency) desired from the bridge.
摘要翻译：用于调整桥接器件性能的方法和装置，包括PCI到PCI桥以及PCI本地总线桥（或主机桥）。本发明的实施例允许根据应用和桥队列大小来调整多总线计算机系统。这些应用程序包括与原始带宽（如磁盘存储）有关的应用程序，以及对延迟敏感（如网络和视频会议）的应用程序。本发明的实施例的特征在于控制寄存器，其指定由桥的读取和写入队列要满足的存储条件。编程的存储条件是触发点，其导致桥接器在读取和写入事务期间将数据传送到队列中或从队列中移除数据，以便提升从桥接器所需的性能（吞吐量或等待时间）。

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