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1. 发明授权

KR101109392B1 Amplifier for microphone 有权
标题翻译：麦克风放大器
公开(公告)号：KR101109392B1
公开(公告)日：2012-01-30
申请号：KR20100070085
申请日：2010-07-20
申请人： KEC KK
发明人： KANG KI TAE
IPC分类号： H03F3/185 , H04R3/00
CPC分类号： H03F3/183 , H03F1/223 , H03F1/56 , H03G1/0029 , H04R3/00
摘要： PURPOSE: A microphone amplifier is provided to turn on the electricity between electrodes by sanctioning the voltage of an input power source in a gate terminal and turning on a JFET and to reduce manufacturing costs. CONSTITUTION: A first condenser and first resistance are serially connected between an input power source and earth. A first JFET(Junction Field Effect Transistor)(J1) interlinks gate terminal to a connecting point of the first resistance and a first condenser. A first BJT(Bipolar Junction Transistor)(Q1) is cascode-connected to the first JFET. A second BJT(Q2) interlinks a base terminal to a first BJT terminal. A second JFET is cascode-connected to the second BJT.
摘要翻译：目的：提供麦克风放大器，通过对栅极端子中的输入电源的电压进行加工并打开JFET并降低制造成本来打开电极之间的电能。构成：第一个电容器和第一个电阻串联在输入电源和地之间。第一JFET（接合场效应晶体管）（J1）将栅极端子与第一电阻的连接点和第一电容器相互连接。第一个BJT（双极结晶体管）（Q1）与第一个JFET共源共栅。第二BJT（Q2）将基站与第一BJT终端相互连接。第二个JFET被共源共栅连接到第二个BJT。

2. 发明授权

KR101906817B1 팝 노이즈를 최소화하거나 또는 제거하기 위한 가변 램프 업/다운 이득을 갖는 증폭기 有权
公开(公告)号：KR101906817B1
公开(公告)日：2018-10-11
申请号：KR1020177013979
申请日：2015-10-22
申请人： 씨러스 로직 인코포레이티드
发明人： 장,링리 , 왕,후안 , 쳉,영지 , 라르센,크리스티안
IPC分类号： H03F3/185 , H03F1/02 , H03F1/30 , H03F3/217
CPC分类号： H03F3/185 , H03F1/0205 , H03F1/305 , H03F3/2171 , H03F2200/03 , H03F2200/351 , H03F2200/375
摘要： 오디오증폭기의사전-전력스테이지블록에서의가변램프업/다운이득은오디오증폭기에의해출력되는청취가능한팝들및 클릭들을감소시키는데사용될수 있다. 제어기는오디오증폭기의동작동안가변램프업/다운이득을조정할수 있다. 가변램프업/다운이득은제어기의제어하에서램프-업및 램프-다운이득을갖는펄스폭 변조(PWM) 변조기/생성기로서구현될수 있다. 가변램프업/다운이득은사전-전력스테이지블록과피드백루프사이의오프셋의트랜지션들을평활하게하며, 이에따라, 오디오증폭기의전력스테이지블록에서증폭되는오프셋을감소시킴으로써청취가능한팝들및 클릭들을감소시킬수 있다.

3. 发明授权

KR101124802B1 전력 배율기 장치 및 방법 有权
标题翻译：功率乘法器装置和方法
公开(公告)号：KR101124802B1
公开(公告)日：2012-03-23
申请号：KR1020077010423
申请日：2005-11-28
申请人： 크리에이티브 테크놀로지 엘티디
发明人： 마키노,준 , 팅,분기
IPC分类号： H03F3/217 , H03F3/185
CPC分类号： H03F3/217 , H03F1/0244 , H03F3/2173 , H03F2200/351
摘要： 증폭기를 위한 전력 배율기 장치가 제공되며, 상기 장치는, 전력 배율기 제어단(power multiplier control stage, 10)과, 증폭기단(amplifier stage, 13)과, 제 1 스위칭단(11)을 포함한다. 상기 제 1 스위칭 단(11)은 상기 전력 배율기 제어단(10)으로 연결되며, 상기 증폭기단(13)이 상기 전력 배율기 제어단(10)으로 연결되며, 상기 전력 배율기 장치는 제 1 출력 단자(1)와 제 2 출력 단자(2)를 포함하고, 상기 제 1 출력 단자(1)와 제 2 출력 단자(2) 사이에 연결되는 부하(@0)를 구동하기 위해, 상기 증폭기단은 상기 제 2 출력 단자로 연결되며, 스위칭가능한 DC 전압 레벨을 상기 제 1 출력 단자로 제공하기 위해, 상기 제 1 스위칭단은 상기 제 1 출력 단자로 연결되는 것을 특징으로 한다. 또한 증폭기 장치의 전력 출력을 증폭하기 위한 방법이 공개된다.

4. 发明授权

KR100875729B1 Mosfet circuit structure and a cmos amplifier employing the circuit structure mosfet 无效
公开(公告)号：KR100875729B1
公开(公告)日：2008-12-26
申请号：KR20070004757
申请日：2007-01-16
IPC分类号： H03F3/45 , H03F3/185
摘要： A MOSFET circuit architecture is provided to improve a glitch characteristic or a low frequency flicker noise characteristic by using a new MOSFET circuit architecture. A MOSFET circuit architecture includes a first signal input unit, a second signal input unit, a first MOSFET(T1), a second MOSFET(T2), a first switching unit(SW11), a second switching unit(SW12), a third switching unit(SW21), and a fourth switching unit(SW22). The first signal input unit receives a first clock signal which is switched at a predetermined period in a VDD-VSS range. The second signal input unit receives a second clock signal having an opposite phase to the first clock signal which is switched at the predetermined period in the VDD-VSS range. The first MOSFET is coupled to the first signal input unit. The second MOSFET is coupled to the second signal input unit. If the first clock signal has a VDD value, the first switching unit connects a source-drain of the first MOSFET. The second switching unit controls the first clock signal to be applied to a drain of the second MOSFET. If the second clock signal has the VDD value, the third switching unit connects a source-drain of the second MOSFET. The fourth switching unit controls the second clock signal to be applied to a drain of the first MOSFET.

5. 发明公开

KR20080067450A MOSFET CIRCUIT ARCHITECTURE AND CMOS AMPLIFIER OF HAVING THE MOSFET CIRCUIT ARCHITECTURE 无效
标题翻译：具有MOSFET电路架构的MOSFET电路架构和CMOS放大器
公开(公告)号：KR20080067450A
公开(公告)日：2008-07-21
申请号：KR20070004757
申请日：2007-01-16
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KOH JEONG WOOK , SUH CHUN DEOK
IPC分类号： H03F3/45 , H03F3/185
CPC分类号： H03F3/45183 , H03F3/45188 , H03K19/00361 , H03K19/018521
摘要： A MOSFET circuit architecture is provided to improve a glitch characteristic or a low frequency flicker noise characteristic by using a new MOSFET circuit architecture. A MOSFET circuit architecture includes a first signal input unit, a second signal input unit, a first MOSFET(T1), a second MOSFET(T2), a first switching unit(SW11), a second switching unit(SW12), a third switching unit(SW21), and a fourth switching unit(SW22). The first signal input unit receives a first clock signal which is switched at a predetermined period in a VDD-VSS range. The second signal input unit receives a second clock signal having an opposite phase to the first clock signal which is switched at the predetermined period in the VDD-VSS range. The first MOSFET is coupled to the first signal input unit. The second MOSFET is coupled to the second signal input unit. If the first clock signal has a VDD value, the first switching unit connects a source-drain of the first MOSFET. The second switching unit controls the first clock signal to be applied to a drain of the second MOSFET. If the second clock signal has the VDD value, the third switching unit connects a source-drain of the second MOSFET. The fourth switching unit controls the second clock signal to be applied to a drain of the first MOSFET.
摘要翻译：提供MOSFET电路架构，通过使用新的MOSFET电路架构来提高毛刺特性或低频闪烁噪声特性。 MOSFET电路结构包括第一信号输入单元，第二信号输入单元，第一MOSFET（T1），第二MOSFET（T2），第一开关单元（SW11），第二开关单元（SW12），第三开关单元（SW21）和第四切换单元（SW22）。第一信号输入单元接收在VDD-VSS范围内以预定周期切换的第一时钟信号。第二信号输入单元接收与在VDD-VSS范围中的预定周期切换的第一时钟信号具有相反相位的第二时钟信号。第一MOSFET耦合到第一信号输入单元。第二MOSFET耦合到第二信号输入单元。如果第一时钟信号具有VDD值，则第一开关单元连接第一MOSFET的源极 - 漏极。第二开关单元控制要施加到第二MOSFET的漏极的第一时钟信号。如果第二时钟信号具有VDD值，则第三开关单元连接第二MOSFET的源极 - 漏极。第四开关单元控制施加到第一MOSFET的漏极的第二时钟信号。

6. 发明授权

KR830001559B1 상보형 MIS증폭회로 失效
公开(公告)号：KR830001559B1
公开(公告)日：1983-08-10
申请号：KR800000395
申请日：1980-02-01
IPC分类号： H03F3/185
摘要： 내용없음.

7. 发明公开

KR830002450A 상보형 MIS 증폭회로 失效
公开(公告)号：KR830002450A
公开(公告)日：1983-05-28
申请号：KR800000395
申请日：1980-02-01
IPC分类号： H03F3/185
摘要： 내용없음

8. 发明公开

KR1020170074236A 팝 노이즈를 최소화하거나 또는 제거하기 위한 가변 램프 업/다운 이득을 갖는 증폭기 审中-实审
标题翻译：放大器具有可变的上升/下降增益，可最大限度地减少或消除爆音
公开(公告)号：KR1020170074236A
公开(公告)日：2017-06-29
申请号：KR1020177013979
申请日：2015-10-22
申请人： 씨러스 로직 인코포레이티드
发明人： 장,링리 , 왕,후안 , 쳉,영지 , 라르센,크리스티안
IPC分类号： H03F3/185 , H03F1/02 , H03F1/30 , H03F3/217
CPC分类号： H03F3/185 , H03F1/0205 , H03F1/305 , H03F3/2171 , H03F2200/03 , H03F2200/351 , H03F2200/375
摘要： 오디오증폭기의사전-전력스테이지블록에서의가변램프업/다운이득은오디오증폭기에의해출력되는청취가능한팝들및 클릭들을감소시키는데사용될수 있다. 제어기는오디오증폭기의동작동안가변램프업/다운이득을조정할수 있다. 가변램프업/다운이득은제어기의제어하에서램프-업및 램프-다운이득을갖는펄스폭 변조(PWM) 변조기/생성기로서구현될수 있다. 가변램프업/다운이득은사전-전력스테이지블록과피드백루프사이의오프셋의트랜지션들을평활하게하며, 이에따라, 오디오증폭기의전력스테이지블록에서증폭되는오프셋을감소시킴으로써청취가능한팝들및 클릭들을감소시킬수 있다.
摘要翻译：音频放大器的预功率级模块中的可变斜坡上升/下降增益可用于减少音频放大器输出的可听到的pop啪声和咔嗒声。控制器可以在音频放大器运行期间调整可变斜坡增/减增益。可变上升/下降增益可以实现为在控制器的控制下具有上升和下降增益的脉宽调制（PWM）调制器/发生器。可变斜坡升/降增益是预先可以减少功率级块和反馈，并通过减少由音频放大器的功率级块放大的偏移平滑的循环，yiettara，可听爆破音之间的偏移的过渡。

9. 发明授权

KR101086064B1 저소비전력 및 고효율 출력형 오디오 앰프 有权
标题翻译：具有低功耗和高效率输出的音频放大器
公开(公告)号：KR101086064B1
公开(公告)日：2011-11-22
申请号：KR1020110061587
申请日：2011-06-24
申请人： 주식회사 동성씨앤티
发明人： 서동목 , 강성모
IPC分类号： H03F3/217 , H03F3/185
CPC分类号： H03F3/2171 , H03F1/0266 , H03F3/185 , H03F2200/03 , H03F2200/444
摘要： PURPOSE: A low dissipation and high efficiency output type audio amplifier is provided to improve the output efficiency of an amplifier itself by steadily activating power amplifier devices. CONSTITUTION: A voltage amplifier(1) amplifies voltage about a minute acoustic signal which is inputted. A output terminal power amplifier(2) amplifies an acoustic signal which is outputted through the voltage amplifier. The amplified acoustic signal is outputted to a speaker(SP). A power voltage supplier(3) supplies voltage for driving each part of an amplifier. A zener diode(ZD1) for power amplifier output voltage detect is connected among resistance for protection(R1), an output port of the power amplifier, and a high voltage output port of the power voltage supplier. A transistor(TR1) for by-pass voltage variableness varies the base bias voltage of a load amount adjustment transistor.
摘要翻译：目的：提供低耗散和高效率的输出型音频放大器，通过稳定地激活功率放大器器件来提高放大器本身的输出效率。构成：电压放大器（1）放大输入的大约一分钟声信号的电压。输出端子功率放大器（2）放大通过电压放大器输出的声信号。放大的声信号被输出到扬声器（SP）。电源供应器（3）提供用于驱动放大器各部分的电压。用于功率放大器输出电压检测的齐纳二极管（ZD1）连接在保护电阻（R1），功率放大器的输出端口和电源供应器的高压输出端口之间。用于旁路电压变化的晶体管（TR1）改变负载量调节晶体管的基极偏置电压。

10. 发明公开

KR1020070084057A 전력 배율기 장치 및 방법 有权
标题翻译：功率乘法器装置和方法
公开(公告)号：KR1020070084057A
公开(公告)日：2007-08-24
申请号：KR1020077010423
申请日：2005-11-28
申请人： 크리에이티브 테크놀로지 엘티디
发明人： 마키노,준 , 팅,분기
IPC分类号： H03F3/217 , H03F3/185
CPC分类号： H03F3/217 , H03F1/0244 , H03F3/2173 , H03F2200/351
摘要： A power multiplier apparatus for an amplifier comprises a power multiplier control stage (10), an amplifier stage (13) and a first switching stage (11) connectable to the power multiplier control stage (10). The amplifier stage (13) is connectable to the power multiplier control stage (10). The power multiplier apparatus has a first output terminal (1) and a second output terminal (2), the amplifier stage (13) is connectable to the second output terminal (2) for driving a load (20) connectable between the first 1 and second (2) output terminals. The first switching stage (11) is connectable to the first output terminal (1) to apply a switchable DC voltage level to the first output terminal (1). There is also disclosed a method of amplifying the power output of an amplifier apparatus.
摘要翻译：用于放大器的功率倍增器装置包括功率乘法器控制级（10），放大级（13）和可连接到功率倍增器控制级（10）的第一开关级（11）。放大器级（13）可连接到功率倍增器控制级（10）。所述功率倍增器装置具有第一输出端子（1）和第二输出端子（2），所述放大器级（13）可连接到所述第二输出端子（2），用于驱动可连接在所述第一输出端子第二（2）个输出端子。第一开关级（11）可连接到第一输出端（1），以向第一输出端（1）施加可切换的直流电压电平。还公开了放大装置的功率放大的放大方法。

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