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    • 6. 发明公开
    • 인쇄회로기판
    • 印刷电路板
    • KR1020140078291A
    • 2014-06-25
    • KR1020120147506
    • 2012-12-17
    • 삼성전기주식회사
    • 조석현
    • H05K1/03H05K3/46
    • H05K1/0271H05K1/0373H05K3/285H05K3/4655H05K2201/068
    • A printed circuit board according to the present invention can reduce warpage deformation due to the difference of the thermal expansion rate of a circuit pattern in the same layer by forming a filling material of a similar thermal expansion rate to the circuit pattern in its surface and between the circuit patterns. Also, a stack body having a lower expansion rate compared to the filling material is formed in one surface of the filling material. Therefore, the entire coefficient of thermal expansion of a PCB is reduced. Because it has a lower coefficient of thermal expansion, it can easily bond an insulating material of little flowability.
    • 根据本发明的印刷电路板可以通过形成与其表面上的电路图案类似的热膨胀率的填充材料,以及在其间的电路图案之间以及在 电路图案。 此外,在填充材料的一个表面中形成具有与填充材料相比较低膨胀率的堆叠体。 因此,PCB的全部热膨胀系数降低。 因为它具有较低的热膨胀系数,所以可以容易地粘结几乎没有流动性的绝缘材料。
    • 7. 发明公开
    • 프린트 배선판
    • 印刷线路板
    • KR1020130034643A
    • 2013-04-05
    • KR1020120109541
    • 2012-09-28
    • 이비덴 가부시키가이샤
    • 아마노데츠오니시와키도시오
    • H05K3/46H05K3/42
    • H05K3/4602H05K1/024H05K3/4655H05K2201/068H05K2201/096
    • PURPOSE: A printed wiring board is provided to prevent a via conductor from being separated from a copper foil, by increasing the thickness of the copper foil of a first conductive layer on a core insulating layer. CONSTITUTION: An interlayer dielectric layer(50A,50C,50E,50G,50I) is laminated on the first surface(F) of a core insulating layer(50M). The interlayer dielectric layer is laminated on the second surface(S) of the core insulating layer. The conductive circuit(58Mb) of the first surface and the conductive circuit(58Ma) of a second surface are connected to a via conductor(60M). The conductive circuit of the first surface includes a copper foil(32) on the core insulating layer, and an electroless plating layer, and an electrolytic plating layer. The conductive circuit(58A) on the interlayer dielectric layer includes a copper foil(42), and an electroless plating layer, and an electrolytic plating layer. The conductive circuit on the interlayer dielectric layer and the conductive circuit on the core insulating layer are connected to a via conductor(60A).
    • 目的:通过增加芯绝缘层上的第一导电层的铜箔的厚度,设置印刷电路板,以防止通孔导体与铜箔分离。 构成:层间绝缘层(50A,50C,50E,50G,50I)层压在芯绝缘层(50M)的第一表面(F)上。 在绝缘层的第二表面(S)层叠有层间电介质层。 第一表面的导电电路(58Mb)和第二表面的导电电路(58Ma)连接到通孔导体(60M)。 第一表面的导电电路包括芯绝缘层上的铜箔(32)和无电镀层以及电解镀层。 层间电介质层上的导电电路(58A)包括铜箔(42),化学镀层和电解镀层。 层间电介质层上的导电电路和芯绝缘层上的导电电路连接到通孔导体(60A)。