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1. 发明授权

KR101597040B1 용량성 신호 소스에 의해 제공된 신호를 증폭하기 위한 시스템 및 집적 회로 有权
标题翻译：用于放大由电容信号源提供的信号的系统和集成电路
公开(公告)号：KR101597040B1
公开(公告)日：2016-02-23
申请号：KR1020140088237
申请日：2014-07-14
申请人： 인피니언 테크놀로지스 아게
发明人： 세발로스조스루이스 , 크롭피치마이클
IPC分类号： H03F1/38 , H03F1/56 , H04R19/04
CPC分类号： H03G7/08 , H03F1/3211 , H03F3/187 , H03F3/45475 , H03F2200/555 , H03F2203/45166 , H03F2203/45526 , H03G3/002 , H03G3/3005 , H03G3/3089 , H03G7/002 , H03G7/06 , H03K5/1532 , H03K5/1536 , H04R3/00 , H04R19/04 , H04R23/00 , H04R2201/003
摘要： 실시예에따르면, 방법은용량성신호소스에의해제공된입력신호의진폭을결정하는단계, 결정된진폭에기초하여압축된아날로그신호를형성하기위해아날로그도메인에서입력신호를압축하는단계, 압축된아날로그신호를압축된디지털신호로변환하는단계, 및압축해제된디지털신호를형성하기위해디지털도메인에서디지털신호를압축해제하는단계를포함한다. 실시예에서, 아날로그신호를압축하는단계는용량성신호소스에커플링된증폭기의제 1 이득을조정하는단계를포함하고, 디지털신호를압축해제하는단계는디지털프로세싱블록의제 2 이득을조정하는단계를포함한다.

2. 发明公开

KR1020090029821A 디지털 필터 장치, 위상 검출 장치, 위치 검출 장치 및 디지털 필터용 프로그램을 수납한 기억 매체 有权
标题翻译：数字滤波器装置，相位检测装置，位置检测装置，AD转换装置，零交叉检测装置和数字滤波器程序
公开(公告)号：KR1020090029821A
公开(公告)日：2009-03-23
申请号：KR1020097002168
申请日：2007-06-14
申请人： 도시바 기카이 가부시키가이샤
发明人： 요꼬까와나루또시 , 사또오쇼오이찌
IPC分类号： G01R19/175 , G01D5/245 , H03K5/26 , H03M1/50
CPC分类号： G01D5/24476 , H03K5/1536 , H03M1/0863 , H03M1/12
摘要： Provided is a digital filter device capable of removing the affect of noise such as chattering from a signal performing zero cross. The digital filter device (4) filters a binary digital signal (DIN) and outputs a binary digital signal (DOUT). The digital filter device (4) includes: a toggle flip-flop (12) which switches the signal level of the digital signal (DOUT) each time a trigger signal is inputted; an XOR circuit (13) which outputs a first enable signal (EN1) while the signal level of the digital signal (DIN) does not coincide with the signal level of the output digital signal (DOUT); and a charge counter (14) which performs counting in synchronization with a clock signal (CLK) while the first enable signal (EN1) is outputted. When the count value has reached an upper limit value, the charge counter (14) resets the count value to an initial value and outputs a carry on signal (ON_RCO) as the trigger signal to the toggle flip-flop (12).
摘要翻译：提供了一种数字滤波器装置，其能够消除诸如来自执行零交叉的信号的颤动的噪声的影响。数字滤波器装置（4）对二进制数字信号（DIN）进行滤波并输出二进制数字信号（DOUT）。数字滤波器装置（4）包括：每次触发信号被输入时切换数字信号（DOUT）的信号电平的开关触发器（12）当数字信号（DIN）的信号电平与输出数字信号（DOUT）的信号电平不一致时，输出第一使能信号（EN1）的异或电路（13）。以及在输出第一使能信号（EN1）的同时执行与时钟信号（CLK）同步的计数的计费计数器（14）。当计数值达到上限值时，计费计数器（14）将计数值复位为初始值，并将进位信号（ON_RCO）作为触发信号输出到触发触发器（12）。

3. 发明公开

KR1020170062428A 전류를 탐지하고 오프셋 전압을 보상하기 위한 방법 및 회로 无效
标题翻译：用于检测电流和补偿偏置电压的方法和电路
公开(公告)号：KR1020170062428A
公开(公告)日：2017-06-07
申请号：KR1020170063972
申请日：2017-05-24
申请人： 세미컨덕터 콤포넨츠 인더스트리즈 엘엘씨
发明人： 프타체크,카렐 , 슈툴러,로만 , 수쿱,프란티세크
IPC分类号： G01R19/175 , H03K5/22
CPC分类号： H03K5/2481 , H03F2203/45212 , H03K5/1536 , H03K5/249
摘要： 제1 및제2 입력들및 출력을갖는래치를포함하는회로. 상기래치의상기출력은상기래치를제어하기위하여피드백구성에연결된다. 상기래치의상기출력이드라이버에연결되고, 상기드라이버의출력은동기식정류트랜지스터를구동한다. 상기회로는, 제1 신호경로를통해상기래치의상기제1 입력에연결되고제2 신호경로를통해상기래치의상기제2 입력에연결되고코일로부터신호를수신하는입력을포함한다.
摘要翻译：以及具有第一和第二输入以及输出的锁存器。锁存器的输出耦合到用于控制锁存器的反馈装置。锁存器的输出连接到驱动器，驱动器的输出驱动同步整流晶体管。该电路包括经由第一信号路径耦合到锁存器的第一输入并经由第二信号路径耦合到锁存器的第二输入并且从线圈接收信号的输入。

4. 发明公开

KR1020150043634A 반도체 장치 审中-实审
标题翻译：半导体器件
公开(公告)号：KR1020150043634A
公开(公告)日：2015-04-23
申请号：KR1020130121898
申请日：2013-10-14
申请人： 에스케이하이닉스 주식회사
发明人： 백승근 , 최훈
IPC分类号： G11C11/4078 , G11C11/40 , G11C7/00
CPC分类号： H03K19/003 , G11C7/1084 , G11C7/1093 , H03K3/0375 , H03K5/08 , H03K5/135 , H03K5/1536 , H04L7/0008
摘要： 외부입력신호의메타-스테이블상태를검출하여메타-스테이블감지신호를생성하기위한메타-스테이블검출부;및상기메타-스테이블감지신호에응답하여상기외부입력신호를선택적으로내부회로로전달하기위한신호전달부를구비하며, 상기메타-스테이블검출부는, 상기외부입력신호를인가받아상기외부입력신호의레벨변환시점을감지하여상태신호를생성하기위한상태신호생성부;및상기상태신호에따라상기외부입력신호의전압레벨과기준레벨을비교하여, 상기외부입력신호의메타-스테이블상태를나타내는메타-스테이블감지신호를출력하는상태판단부를포함하는반도체장치가제공되며, 이에의해낮은소비전력으로입력신호의메타-스테이블상태를판단할수 있다.
摘要翻译：提供一种半导体器件，包括：元稳定检测单元，用于通过检测外部输入信号的元稳定状态来产生金属稳定的感测信号; 以及信号发送单元，其通过响应所述元稳定感测信号来选择性地将所述外部输入信号发送到内部电路，其中所述元稳定检测单元包括：条件信号生成单元，通过接收外部输入信号来产生条件信号和感应电平转换点的外部输入信号; 以及条件决定单元，通过根据条件信号比较外部输入信号的电压电平和参考电平，输出显示外部输入信号的元稳定状态的元稳定感测信号。因此，可以以低功耗决定输入信号的元稳定状态。

5. 发明公开

KR1020050013088A 트랜지스터의 문턱전압 변화를 보상한 비교기 및 보상회로 失效
标题翻译：用于补偿用于补偿输出偏移量的晶体管阈值电压变化的比较器和补偿电路
公开(公告)号：KR1020050013088A
公开(公告)日：2005-02-02
申请号：KR1020040110313
申请日：2004-12-22
申请人： 한양대학교 산학협력단
发明人： 유창식 , 이균렬
IPC分类号： H03K5/22
CPC分类号： H03K5/2472 , H03F3/45183 , H03K5/1536
摘要： PURPOSE: A comparator and a compensation circuit for compensating a variation of a threshold voltage of a transistor are provided to compensate an offset due to the variation of the threshold voltage generated from a transistor within a comparator. CONSTITUTION: A prior signal amplifier(210) includes a plurality of transistors for amplifying a current signal and mirroring the current signal, and a threshold voltage compensator coupled to one of the transistors in order to mirror two current signals corresponding to each voltage signal received from a first input terminal and a second input terminal. A signal compensation unit(230) includes a transistor mirrored by the current signal of the prior amplifier, a transistor for amplifying and comparing the received current signals, and a threshold voltage compensator connected to one of the transistors in order to output two voltage signals corresponding to the current signals. A logic circuit(250) is used for outputting one voltage signal corresponding to the voltage signals of the signal compensation unit.
摘要翻译：目的：提供用于补偿晶体管的阈值电压变化的比较器和补偿电路，以补偿由比较器内的晶体管产生的阈值电压的变化引起的偏移。构成：现有信号放大器（210）包括用于放大电流信号和镜像电流信号的多个晶体管，以及耦合到晶体管之一的阈值电压补偿器，以便镜像对应于从第一输入端子和第二输入端子。信号补偿单元（230）包括由现有放大器的电流信号反映的晶体管，用于放大和比较接收到的电流信号的晶体管和连接到晶体管之一的阈值电压补偿器，以便输出相应的两个电压信号到当前信号。逻辑电路（250）用于输出与信号补偿单元的电压信号对应的一个电压信号。

6. 发明公开

KR1020140096015A 용량성 신호 소스에 의해 제공된 신호를 증폭하기 위한 시스템 및 집적 회로 有权
标题翻译：用于放大由电容信号源提供的信号的系统和集成电路
公开(公告)号：KR1020140096015A
公开(公告)日：2014-08-04
申请号：KR1020140088237
申请日：2014-07-14
申请人： 인피니언 테크놀로지스 아게
发明人： 세발로스조스루이스 , 크롭피치마이클
IPC分类号： H03F1/38 , H03F1/56 , H04R19/04
CPC分类号： H03G7/08 , H03F1/3211 , H03F3/187 , H03F3/45475 , H03F2200/555 , H03F2203/45166 , H03F2203/45526 , H03G3/002 , H03G3/3005 , H03G3/3089 , H03G7/002 , H03G7/06 , H03K5/1532 , H03K5/1536 , H04R3/00 , H04R19/04 , H04R23/00 , H04R2201/003 , H03F1/38 , H03F1/56 , H03F3/2175
摘要： According to an embodiment, a method includes a step of determining the amplitude of an input signal provided by a capacitive signal source, a step of compressing the input signal in an analog domain for forming a compressed analog signal based on the determined amplitude, a step of changing the compressed analog signal into a compressed digital signal, and a step of decompressing the digital signal in the digital domain for forming the decompressed digital signal. In an embodiment, a step of compressing an analog signal includes a step of controlling the first gain of an amplifier coupled with a capacitive signal source, and a step of decompressing a digital signal includes a step of controlling the second gain of digital processing block.
摘要翻译：根据实施例，一种方法包括确定由电容信号源提供的输入信号的幅度的步骤，基于所确定的幅度来压缩模拟域中的输入信号以形成压缩模拟信号的步骤，步骤将压缩的模拟信号改变为压缩数字信号，以及对数字域中的数字信号进行解压缩以形成解压缩的数字信号的步骤。在一个实施例中，压缩模拟信号的步骤包括控制与电容性信号源耦合的放大器的第一增益的步骤，并且解码数字信号的步骤包括控制数字处理块的第二增益的步骤。

7. 发明公开

KR1020130116812A 용량성 신호 소스에 의해 제공된 신호를 증폭하는 방법 有权
标题翻译：高输入电容信号放大器的系统与方法
公开(公告)号：KR1020130116812A
公开(公告)日：2013-10-24
申请号：KR1020130040733
申请日：2013-04-15
申请人： 인피니언 테크놀로지스 아게
发明人： 세발로스조스루이스 , 크롭피치마이클
IPC分类号： H03F1/38 , H03F1/56 , H04R19/04
CPC分类号： H03G7/08 , H03F1/3211 , H03F3/187 , H03F3/45475 , H03F2200/555 , H03F2203/45166 , H03F2203/45526 , H03G3/002 , H03G3/3005 , H03G3/3089 , H03G7/002 , H03G7/06 , H03K5/1532 , H03K5/1536 , H04R3/00 , H04R19/04 , H04R23/00 , H04R2201/003
摘要： PURPOSE: A system and a method for high input capacitive signal amplifier are provided to maintain the large dynamic range of a capacitive signal source like microphones. CONSTITUTION: A variable gain amplifier (106) has at least one stage for amplification of the output of a micro-electro-mechanical systems (MEMS) microphone (102) coupled to an integrated circuit (IC) (100) through an input pad (116). A signal detection and level adaptation block (112) measures amplitude in the output of the variable gain amplifier and calculates gain control signals (GC1,GC2) as the function of the measured amplitude. An analog to digital converter (ADC) (108) is implemented using an audio oversampling data converter such as a sigma-delta ADC. A bias generator (104) provides bias voltage for the microphone itself to a pin (117). [Reference numerals] (104) Bias voltage generator; (112) Signal detection and level adaptation block; (114) Digital interface
摘要翻译：目的：提供一种用于高输入电容信号放大器的系统和方法，以保持像麦克风这样的电容信号源的大动态范围。构成：可变增益放大器（106）具有至少一个级，用于通过输入焊盘（...）放大耦合到集成电路（IC）（100）的微电子机械系统（MEMS）麦克风（102）的输出， 116）。信号检测和电平调整块（112）测量可变增益放大器的输出中的幅度，并将增益控制信号（GC1，GC2）作为测量幅度的函数进行计算。使用诸如Σ-ΔADC之类的音频过采样数据转换器来实现模数转换器（ADC）（108）。偏置发生器（104）为麦克风本身提供针脚（117）的偏置电压。（附图标记）（104）偏置电压发生器; （112）信号检测和电平调整块; （114）数字接口

8. 发明授权

KR101061340B1 디지털 필터 장치, 위상 검출 장치, 위치 검출 장치 및 디지털 필터용 프로그램을 수납한 기억 매체 有权
标题翻译： 디지털터터장치，위상검출장치，위치검출장치및소지털터용프로그램을수납한기억매체
公开(公告)号：KR101061340B1
公开(公告)日：2011-08-31
申请号：KR1020097002168
申请日：2007-06-14
申请人： 도시바 기카이 가부시키가이샤
发明人： 요꼬까와나루또시 , 사또오쇼오이찌
IPC分类号： G01R19/175 , G01D5/245 , H03K5/26 , H03M1/50
CPC分类号： G01D5/24476 , H03K5/1536 , H03M1/0863 , H03M1/12
摘要： A digital filter device capable of removing the effect of noise such as chattering from a zero crossing signal is provided. A digital filter device 4 filtering a binary digital signal DIN and outputting a binary digital signal DOUT is provided with a toggle flip-flop 12 which switches a signal level of the digital signal DOUT each time a trigger signal is input; an XOR circuit 13 which outputs a first enable signal EN1 while a signal level of the digital signal DIN does not match with the signal level of the output digital signal DOUT; and a charge counter 14 which counts in synchronization with a clock signal CLK while the first enable signal EN1 is input and resets the count to an initial value and outputs a carry on signal ON_RCO as the trigger signal to the toggle flip-flop 12 when the count has reached an upper limit value.
摘要翻译：提供了一种能够消除诸如来自零交叉信号的抖动之类的噪声影响的数字滤波器装置。数字滤波器装置4对二进制数字信号DIN进行滤波并输出二进制数字信号DOUT，该数字滤波器装置4设置有触发器12，该触发器在每次输入触发信号时切换数字信号DOUT的信号电平; XOR电路13，其在数字信号DIN的信号电平与输出数字信号DOUT的信号电平不匹配的情况下输出第一使能信号EN1; 以及当第一使能信号EN1被输入时与时钟信号CLK同步计数的充电计数器14，并且将该计数重置为初始值，并且当触发信号ON_RCO作为触发信号输出到触发触发器12时计数已达到上限值。

9. 发明公开

KR1020110027600A 전류를 탐지하고 오프셋 전압을 보상하기 위한 방법 및 회로 有权
标题翻译：用于检测电流和电压的电流和补偿的方法
公开(公告)号：KR1020110027600A
公开(公告)日：2011-03-16
申请号：KR1020100087776
申请日：2010-09-08
申请人： 세미컨덕터 콤포넨츠 인더스트리즈 엘엘씨
发明人： 프타체크,카렐 , 슈툴러,로만 , 수쿱,프란티세크
IPC分类号： G01R19/175 , H03K5/22
CPC分类号： H03K5/2481 , H03F2203/45212 , H03K5/1536 , H03K5/249 , G01R19/175 , H03K5/22
摘要： PURPOSE: A method for detecting a current and compensating for an offset voltage and a circuit is provided to set turn-off threshold voltage by detecting zero current conditions and initializing offset. CONSTITUTION: In a method for detecting a current and compensating for an offset voltage and a circuit, a first comparator(10) comprises first and second input terminals and an output terminal. A second comparator(20) comprises a first to third input terminal and an output terminal. The first terminal of the first comparator is connected to the second terminal of the second comparator. A first logic circuit comprises first and the second input terminal and an output terminal. A driver circuit(46) comprises an input terminal and an output terminal.
摘要翻译：目的：提供一种检测电流和补偿偏置电压和电路的方法，通过检测零电流条件和初始化偏移来设置关断阈值电压。构成：在用于检测电流并补偿偏置电压和电路的方法中，第一比较器（10）包括第一和第二输入端子和输出端子。第二比较器（20）包括第一至第三输入端和输出端。第一比较器的第一端连接到第二比较器的第二端。第一逻辑电路包括第一和第二输入端和输出端。驱动电路（46）包括输入端和输出端。

10. 发明授权

KR101876459B1 전류를 탐지하고 오프셋 전압을 보상하기 위한 방법 및 회로 有权
公开(公告)号：KR101876459B1
公开(公告)日：2018-07-10
申请号：KR1020180035848
申请日：2018-03-28
申请人： 세미컨덕터 콤포넨츠 인더스트리즈 엘엘씨
发明人： 프타체크,카렐 , 슈툴러,로만 , 수쿱,프란티세크
IPC分类号： G01R19/175 , H03K5/22
CPC分类号： H03K5/2481 , H03F2203/45212 , H03K5/1536 , H03K5/249
摘要： 제1 및제2 입력들및 출력을갖는래치를포함하는회로. 상기래치의상기출력은상기래치를제어하기위하여피드백구성에연결된다. 상기래치의상기출력이드라이버에연결되고, 상기드라이버의출력은동기식정류트랜지스터를구동한다. 상기회로는, 제1 신호경로를통해상기래치의상기제1 입력에연결되고제2 신호경로를통해상기래치의상기제2 입력에연결되고코일로부터신호를수신하는입력을포함한다.

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