专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

KR20070079115A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：KR20070079115A
公开(公告)日：2007-08-06
申请号：KR20060009536
申请日：2006-02-01
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： NOH JIN TAE , YANG SANG RYOL , HWANG KI HYUN , KIM JIN GYUN , LEE SUNG HAE , KIM HONG SUK
IPC分类号： H01L21/336
摘要： A method for manufacturing a semiconductor device is provided to control effectively off-current of a cell transistor by increasing a work function of a gate electrode. A gate insulating layer(102) and a polysilicon layer doped with a P type impurity are formed on a substrate(100) including a cell area having a pin type active area and a peri/core area including a flat type active area. A photoresist pattern for exposing an NMOS transistor region of the peri/core area is formed on the polysilicon layer doped with the P type impurity. The exposed polysilicon layer is converted to an N type impurity-doped polysilicon layer by counter-doping an N type impurity on the polysilicon layer. A first polysilicon pattern(110) doped with the P type impurity, a second polysilicon pattern(112) doped with the P type impurity, and a third polysilicon pattern(114) doped with the N type impurity are formed by patterning the polysilicon layer doped with the P type impurity and the N type impurity. Source/drains are formed at both sides of the first to the third polysilicon patterns.
摘要翻译：提供一种用于制造半导体器件的方法，通过增加栅电极的功函数来有效地控制单元晶体管的截止电流。在包括具有引脚型有源区域的单元区域和包括平面型有源区域的区域/核心区域的基板（100）上形成栅极绝缘层（102）和掺杂有P型杂质的多晶硅层。在掺杂有P型杂质的多晶硅层上形成用于暴露周边/核心区域的NMOS晶体管区域的光致抗蚀剂图案。曝光的多晶硅层通过在多晶硅层上相互掺杂N型杂质而转换成N型杂质掺杂多晶硅层。掺杂有P型杂质的第一多晶硅图案（110），掺杂有P型杂质的第二多晶硅图案（112）和掺杂有N型杂质的第三多晶硅图案（114）通过将多晶硅层掺杂具有P型杂质和N型杂质。源极/漏极形成在第一至第三多晶硅图案的两侧。

IPRDB

热门服务

关于我们

友情链接

联系方式