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1. 发明公开

KR20100079393A Semiconductor memory devices and methods of forming the same 有权
标题翻译：半导体存储器件及其形成方法
公开(公告)号：KR20100079393A
公开(公告)日：2010-07-08
申请号：KR20080137864
申请日：2008-12-31
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM JIN GYUN , LEE MYOUNG BUM , HWANG KI HYUN
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L21/28273 , H01L21/28282 , H01L27/11551 , H01L27/11578
摘要： PURPOSE: A semiconductor memory devices and a method of forming the same are provided to improve the reliability of a semiconductor memory by minimizing the off-leakage current of first and second selection transistors. CONSTITUTION: Insulating layers and cell gate layers are formed on a substrate alternately. Cell gate layers and insulating layers are continuously patterned form an opening. A conductive barrier(150) is formed on side wall of gate layer inside the opening through a nitration process. A block insulating layer and a charge storage layer, and a tunnel layer(160) are formed on the side walls of the conductive barrier layer and the insulating layer inside the opening.
摘要翻译：目的：提供半导体存储器件及其形成方法，以通过最小化第一和第二选择晶体管的漏电流来提高半导体存储器的可靠性。构成：交替地在基板上形成绝缘层和电池栅极层。电池栅极层和绝缘层从开口连续地图案化。通过硝化工艺在开口内的栅极层的侧壁上形成导电屏障（150）。在导电阻挡层的侧壁和开口内部的绝缘层的侧壁上形成有块绝缘层和电荷存储层以及隧道层（160）。

2. 发明公开

KR20180018258A 박막의 제조 방법 审中-公开
标题翻译：制造薄膜的方法
公开(公告)号：KR20180018258A
公开(公告)日：2018-02-21
申请号：KR20170021324
申请日：2017-02-17
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM JIN GYUN
IPC分类号： H01L21/02 , H01L21/205
CPC分类号： H01L21/02252 , C23C16/308 , C23C16/345 , C23C16/401 , C23C16/455 , C23C16/45523 , C23C16/505 , C23C16/52 , C23C16/56 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/02332 , H01L21/0234 , H01L22/26
摘要： 박막의제조방법이제공된다. 박막의제조방법은, 단위싸이클공정을반복적으로수행하여소정의두께(predetermined thickness)를갖는박막을형성하는것을포함하는박막의제조방법으로, 단위싸이클공정은, 제조장비의제1 챔버에서, 웨이퍼상에예비박막층을형성하고, 제조장비의제2 챔버에서, 예비박막층을완전히(completely) 변환하여웨이퍼상에박막층을형성하는것을포함하고, 예비박막층을형성하는것은, 실리콘막의증착및 산화공정을반복적으로수행하여예비박막층을형성하거나, 또는실리콘막의증착및 질화공정을반복적으로수행하여예비박막층을형성하는것을포함하고, 박막층은, 단위싸이클공정을반복적으로수행하여이전에형성된박막층상에반복적으로형성된다.
摘要翻译：重复执行单位循环过程以形成具有预定厚度的薄膜。在单位循环过程中，在晶片上形成预备膜层，并且通过将预备膜层转换成薄膜层而在晶片上形成薄膜层。在反复执行单位循环过程中预先形成的薄膜层上重复形成薄膜层。

3. 发明公开

KR20100075098A Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：KR20100075098A
公开(公告)日：2010-07-02
申请号：KR20080133714
申请日：2008-12-24
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM JIN GYUN , SHIN SEUNG MOK , CHAE SOO DOO , LEE SEUNG YUP
IPC分类号： H01L27/115
CPC分类号： H01L27/11551 , H01L27/0688 , H01L27/11548 , H01L27/11556 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/42332 , H01L29/7881 , H01L29/792 , H01L29/7926 , H01L27/2463
摘要： PURPOSE: A nonvolatile memory device is provided to improve the reliability of a nonvolatile memory cell by preventing charges stored in a charge storage pattern from moving up and down. CONSTITUTION: A plurality of gate patterns and Insulation patterns between a plurality of gates are alternatively stacked on a substrate. An active pattern(140a) is arranged on a substrate and is extended along the sidewalls of the cell gate patterns and the insulation patterns between the gates. A plurality of charge storage patterns is arranged between the plurality of cell gate patterns and an active pattern and is separated with each other. Tunnel insulation patterns are arranged between the plurality of charge storage patterns and the active pattern and are directly connected to each other. A plurality of blocking insulation patterns is interposed between the plurality of cell gate patterns and the plurality of charge storage patterns.
摘要翻译：目的：提供一种非易失性存储装置，通过防止存储在电荷存储模式中的电荷上下移动来提高非易失性存储单元的可靠性。构成：在多个栅极之间的多个栅极图案和绝缘图案交替地层叠在基板上。有源图案（140a）布置在衬底上并沿着单元栅极图案的侧壁和栅极之间的绝缘图案延伸。多个电荷存储图案被布置在多个单元栅极图案和活动图案之间并且彼此分离。隧道绝缘图案布置在多个电荷存储图案和有源图案之间并且彼此直接连接。多个隔离绝缘图案插入在多个单元栅极图案和多个电荷存储图案之间。

4. 发明公开

KR20070079115A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：KR20070079115A
公开(公告)日：2007-08-06
申请号：KR20060009536
申请日：2006-02-01
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： NOH JIN TAE , YANG SANG RYOL , HWANG KI HYUN , KIM JIN GYUN , LEE SUNG HAE , KIM HONG SUK
IPC分类号： H01L21/336
摘要： A method for manufacturing a semiconductor device is provided to control effectively off-current of a cell transistor by increasing a work function of a gate electrode. A gate insulating layer(102) and a polysilicon layer doped with a P type impurity are formed on a substrate(100) including a cell area having a pin type active area and a peri/core area including a flat type active area. A photoresist pattern for exposing an NMOS transistor region of the peri/core area is formed on the polysilicon layer doped with the P type impurity. The exposed polysilicon layer is converted to an N type impurity-doped polysilicon layer by counter-doping an N type impurity on the polysilicon layer. A first polysilicon pattern(110) doped with the P type impurity, a second polysilicon pattern(112) doped with the P type impurity, and a third polysilicon pattern(114) doped with the N type impurity are formed by patterning the polysilicon layer doped with the P type impurity and the N type impurity. Source/drains are formed at both sides of the first to the third polysilicon patterns.
摘要翻译：提供一种用于制造半导体器件的方法，通过增加栅电极的功函数来有效地控制单元晶体管的截止电流。在包括具有引脚型有源区域的单元区域和包括平面型有源区域的区域/核心区域的基板（100）上形成栅极绝缘层（102）和掺杂有P型杂质的多晶硅层。在掺杂有P型杂质的多晶硅层上形成用于暴露周边/核心区域的NMOS晶体管区域的光致抗蚀剂图案。曝光的多晶硅层通过在多晶硅层上相互掺杂N型杂质而转换成N型杂质掺杂多晶硅层。掺杂有P型杂质的第一多晶硅图案（110），掺杂有P型杂质的第二多晶硅图案（112）和掺杂有N型杂质的第三多晶硅图案（114）通过将多晶硅层掺杂具有P型杂质和N型杂质。源极/漏极形成在第一至第三多晶硅图案的两侧。

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