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1. 发明公开

KR20090033674A DIGIT REVERSING APPARATUS FOR FIXED-LENGTH AND VARIABLE-LENGTH RADIX-4 FFT 无效
标题翻译：固定长度和可变长度RADIX-4 FFT的数字反转装置
公开(公告)号：KR20090033674A
公开(公告)日：2009-04-06
申请号：KR20070098828
申请日：2007-10-01
申请人： KOREA ELECTRONICS TELECOMM , KYUNGPOOK NAT UNIV IND ACAD
发明人： OCK SEUNG HO , MOON BYUNG IN , KIM CHANG SUN , CHA JIN JONG , YOON BYOUNG JIN
IPC分类号： H03K23/00
CPC分类号： G06F7/768 , G06F17/142 , H03K21/026
摘要： A digit revering apparatus for the fixed length and variable length radix-4 fast fourier transform is provided to minimizes a digit reversing speed and a hardware area by performing the high data reversing by the simple hardware even though the size of the fast fourier transform is increased. A first counter module(100) generates an upper 2 bit address in response to a first clock signal. A first clock selector(300) selectively outputs a first clock signal to the first counter module in response to the selection signal. A second clock selector(310) generates a second clock signal by logic-combining the upper 2 bit address and outputs one of the first and second clock signals in response to a selection signal. The second counter module generates a lower 2 bit address in response to the output of the second clock selector.
摘要翻译：提供固定长度和可变长度的基数4快速傅立叶变换的数字返回装置，用于通过简单硬件执行高数据反转来最小化数字反转速度和硬件区域，即使快速傅里叶变换的大小增加。第一计数器模块（100）响应于第一时钟信号产生高2位地址。第一时钟选择器（300）响应于选择信号选择性地将第一时钟信号输出到第一计数器模块。第二时钟选择器（310）通过逻辑组合高2位地址产生第二时钟信号，并响应于选择信号输出第一和第二时钟信号之一。第二计数器模块响应于第二时钟选择器的输出而产生较低的2位地址。

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