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1. 发明授权

KR100850351B1 베이스 인터페이스를 통한 ＡＴＣＡ 시스템의 이중화 구현방법 및 이를 구현한 ＡＴＣＡ 시스템 失效
标题翻译：通过基本接口提供ATCA系统冗余结构的方法
公开(公告)号：KR100850351B1
公开(公告)日：2008-08-04
申请号：KR1020060062677
申请日：2006-07-04
申请人： 한국전자통신연구원
发明人： 김용태 , 이상연 , 송광석 , 김봉태
IPC分类号： H04L12/24 , H04L12/28 , H04L12/56
摘要： 본 발명은 IPC 통신을 위해 정의된 베이스 인터페이스를 통해 표준화된 ATCA 규격의 범위 내에서 이중화를 구현할 수 있는 베이스 인터페이스를 통한 ATCA 시스템의 이중화 구현 방법 및 이를 적용한 ATCA 시스템에 관한 것으로서, ATCA 시스템에 구비되는 라우팅 프로토콜 보드, 라인보드가 각각 상기 베이스 인터페이스에서 제공되는 2개의 IPC 경로에 연결되는 두 개의 포트를 구비하고 있어, 상기 두 포트중 사용할 포트에 대표 IP 주소를 할당한 후, 상기 대표 IP 주소를 이용하여 IPC 통신을 수행하면서, 포트에러 및 링크 다운이 발생되는 경우 다른 포트에 상기 대표 IP 주소를 부여함으로써, 안정된 IPC 통신을 수행할 수 있도록 하며, 보드관리제어기(ShMC)의 단중화된 IPC 경로의 취약점을 보충하고자, 액티브 상태의 보드관리제어기에서 포트 에러 및 링크 다운이 발생하는 경우 스탠바이 상태의 보드관리제어기를 경유한 IPC 경로를 제공한 것이다.
ATCA, 라우팅 프로토콜(RP) 보드, 프로세서간 통신(IPC) 보드, 스위치 패브릭(SF) 보드, 보드관리제어기(ShMC), 이중화, 베이스 인터페이스

2. 发明授权

KR100748087B1 에스.피이.아이(ＳＰＩ) 스위치를 이용한 고속 패킷 정합장치 및 그 초기화 방법 失效
标题翻译：用于使用SPI开关的超额订购者的高速分组接口设备及其初始化方法
公开(公告)号：KR100748087B1
公开(公告)日：2007-08-09
申请号：KR1020050108606
申请日：2005-11-14
申请人： 한국전자통신연구원
发明人： 두경환 , 송광석 , 김봉태
IPC分类号： H04N7/12
摘要： 본 발명은 시스템의 실제 처리 트래픽 용량을 높이고 링크 안정화를 구현하기 위해 트래픽 처리 용량 이상의 물리포트를 수용하는 고속 패킷 정합 장치에 관한 것으로서, 물리계층으로부터 인가되는 아날로그 신호를 디지털로 변환하고, 내부 디지털 신호를 아날로그 신호로 변환하여 출력하는 적어도 하나 이상의 트랜시버; 각 물리 계층에 접속되는 프로토콜 종류에 따라 해당 프로토콜 패킷 프레임으로 생성 및 복원 기능을 수행하고 상기 트랜시버에 각각 대응되게 구성되는 적어도 하나 이상의 프레이머; 및 상기 프레이머들로부터 수신되는 패킷을 다중화하고, 가입자로부터 송신되는 패킷을 해당 목적지로 전달하기 위한 경로에 있는 프레이머로 연결하는 물리 계층 입출력 다중화부를 포함하여 구성된다.
SPI, 기가비트, 인터페이스, 물리계층, 패킷 정합, 플랫폼

3. 发明公开

KR1020070059737A ＡＴＣＡ 플랫폼을 위한 고성능 패킷 스위칭 장치 및 방법 失效
标题翻译：用于使用ATCA平台切换分组数据的装置和方法
公开(公告)号：KR1020070059737A
公开(公告)日：2007-06-12
申请号：KR1020050118932
申请日：2005-12-07
申请人： 한국전자통신연구원
发明人： 최병철 , 송광석 , 김봉태
IPC分类号： H04L12/931
CPC分类号： H04L49/552 , H04L49/101
摘要： A high-performance packet switching device for an ATCA(Advanced Telecom Computing Architecture) platform and a method thereof are provided to conduct a high-performance packet switching function between plural packet processing devices as complying with an ATCA backplane standard, and to realize a duplexing function, thereby ensuring high reliability on packet delivery paths. A packet switching unit(404) exchanges packets with each packet processing device mounted on a node slot of an ATCA platform through a fabric interface defined on an ATCA. A switch controller(400) collects a lot of configuration and state information for the packet switching unit, and controls the collected information. A duplexing and DMA(Direct Memory Access) controller(403) changes data received from the switch controller into serial data to deliver the serial data to the switching unit, and changes the serial data into parallel data for a DMA operation, then delivers the parallel data to the controller.
摘要翻译：提供了一种用于ATCA（高级电信计算架构）平台的高性能分组交换设备及其方法，用于在符合ATCA背板标准的多个分组处理设备之间进行高性能分组交换功能，并实现双工功能，从而确保分组传送路径的高可靠性。分组交换单元（404）通过在ATCA上定义的结构接口与安装在ATCA平台的节点槽上的每个分组处理设备交换分组。开关控制器（400）收集分组交换单元的大量配置和状态信息，并控制收集的信息。双工和DMA（直接存储器访问）控制器（403）将从交换机控制器接收的数据变换为串行数据，将串行数据传送到交换单元，并将串行数据更改为并行数据进行DMA操作，然后传送并行数据到控制器。

4. 发明授权

KR100655599B1 노드별 20Ｇｂｐｓ 패킷 스위칭 대역폭을 지원하는ＡＴＣＡ 플랫폼 장치 失效
标题翻译： 노드별20Gbps패킷스위칭대역폭을지원하는ATCA플랫폼장노
公开(公告)号：KR100655599B1
公开(公告)日：2006-12-08
申请号：KR1020050105303
申请日：2005-11-04
申请人： 한국전자통신연구원
发明人： 최병철 , 송광석 , 김봉태
IPC分类号： H04L12/771
摘要： An ATCA(Advanced Telecom Computing Architecture) platform device for supporting 20Gbps packet switching bandwidths to each node is provided to allocate separate additional packet delivery path signals by expanding fabric interfaces in a zone 3 of a packet switch, thus packet switching at 20Gbps speed per port of the packet switches is available. Packet switches(101) provide fabric interfaces with plural packet processors(102,103). The packet processors(102,103) determine delivery paths to a next hop for externally received IP(Internet Protocol) packets, change packet headers to deliver the changed headers to the packet switches(101), and reassemble packets received from the switches(101) as controlling packet traffic for sending the packets. Switch expanding units indirectly connect the switches(101) with the processors(102,103), and provide expansive functions of the fabric interfaces between the switches(101) and the processors(102,103).
摘要翻译：提供了用于支持20Gbps分组交换带宽到每个节点的ATCA（高级电信计算架构）平台设备，以通过扩展分组交换机的区域3中的结构接口来分配单独的附加分组传递路径信号，从而以每端口20Gbps的速度进行分组交换的分组交换机可用。分组交换机（101）为多个分组处理器（102,103）提供结构接口。分组处理器（102,103）为外部接收到的IP（因特网协议）分组确定到下一跳的传送路径，改变分组报头以将改变的报头递送给分组交换机（101），并将从交换机（101）接收的分组重新组合为控制用于发送分组的分组业务。交换扩展单元间接连接交换机（101）和处理器（102,103），并提供交换机（101）和处理器（102,103）之间的交换接口的扩展功能。

5. 发明公开

KR1020030013198A 컴퓨터 시스템의 고장 감내 방법 无效
标题翻译：计算机系统容错方法
公开(公告)号：KR1020030013198A
公开(公告)日：2003-02-14
申请号：KR1020010047557
申请日：2001-08-07
申请人： 한국전자통신연구원 , 주식회사 케이티
发明人： 정우석 , 송광석 , 박승범 , 박동선
IPC分类号： G06F11/00
摘要： PURPOSE: A method for a fault tolerant of a computer system is provided to embody a system easily and endow an effective fault tolerant ability at low cost by suggesting a fault tolerant technique based on a software. CONSTITUTION: If a message is not received from a job execution processor(12,501), a sensing processor(14) which does not receive a message for a defined time transmits a message for informing a non-operation of the job execution processor(12) to a main processor(11,502). The main processor(11) checks an existence or not of the job execution processor(12,503). The main processor(11) transmits a KILL message to the job execution processor(12) against an emergency(504). The main processor(11) transmits a message for operating a waiting processor(13) as a job execution processor to the waiting processor(13,505). The main processor(11) creates new waiting processor(16,506). A communication is performed between new job execution processor(13) and the sensing processor(14).
摘要翻译：目的：提供一种容错计算机系统的方法，通过提出基于软件的容错技术，轻松实现系统，以低成本赋予有效的容错能力。构成：如果没有从作业执行处理器（12,501）接收到消息，则在定义的时间内没有接收到消息的感测处理器（14）发送用于通知作业执行处理器（12）的不操作的消息，到主处理器（11,502）。主处理器（11）检查作业执行处理器（12,503）的存在与否。主处理器（11）针对紧急情况向作业执行处理器（12）发送KILL消息（504）。主处理器（11）将作为作业执行处理器的等待处理器（13）操作的消息发送到等待处理器（13505）。主处理器（11）创建新的等待处理器（16,506）。在新的作业执行处理器（13）和感测处理器（14）之间进行通信。

6. 发明授权

KR100371136B1 이중포트메모리를 사용한 메시지 버퍼 풀 감지 및 관리 방법 失效
标题翻译： 이중포트메모리를사용한메시지버퍼풀감지및관리방
公开(公告)号：KR100371136B1
公开(公告)日：2003-02-07
申请号：KR1019990056358
申请日：1999-12-10
申请人： 한국전자통신연구원 , 주식회사 케이티
发明人： 박혜숙 , 문승진 , 송광석
IPC分类号： H04L12/861 , H04L12/931 , H04L12/26
摘要： PURPOSE: A method for sensing and managing message buffer pull using a dual port ram is provided to instantly sense buffer full by transmitting and receiving control information between a master board and a slaver board via a DPRAM and reduce load of a processor by reporting buffer full or termination mutually. CONSTITUTION: Functions of a master board and a slaver board are initialized(S310). The master board is operated as master basic functions of sensing obstacles and managing the slaver board, transmitting a message to the slaver board, and receiving the message from the slaver board(S320-S323). The master board confirms the method for sensing buffer full in methods 1 and 2 before transmitting the message(S330). If method 1 is set up, the master board reads current transmission buffer write pointer(TXWP) in a control information area for confirming whether buffer flag of the corresponding write pointer is empty(S340). If empty, the master board stores the message in a transmission buffer indicated by the TXWP and changes the flag from empty to use(S390). The master board increases the value of the TXWP and changes the TXWP value with a transmission starting address(TXSA)(S391). If not empty, the master board generates transmission buffer full interrupt to the slaver board(S370) and waits in idle state(S371). If the master board receives buffer full termination interrupt(S380), the master board reopens message transmission. If method 2 is set up, the master board reads transmission buffer and read and write pointers and calculates the number of the empty buffers for calculating buffer full degree(S350). The master board compares the set reference value with the buffer full degree for judging buffer full(S360).
摘要翻译：目的：提供一种使用双端口RAM来感测和管理消息缓冲器拉动的方法，以通过DPRAM在主板和奴隶板之间发送和接收控制信息来立即感测缓冲器已满，并通过报告缓冲器已满而减少处理器的负载或相互终止。组成：主板和奴隶板的功能被初始化（S310）。主板作为感应障碍物和管理奴隶板的主要基本功能，向奴隶板发送消息，并从奴隶板接收消息（S320-S323）。主板在发送消息之前确认用于在方法1和2中感测缓冲器满的方法（S330）。如果设置了方法1，主板读取控制信息区域中的当前发送缓冲器写入指针（TXWP），以确认相应写入指针的缓冲标志是否为空（S340）。如果为空，则主控板将该消息存储在由TXWP指示的发送缓冲器中，并将标志从空改变为使用（S390）。主板增加TXWP的值并用发送起始地址（TXSA）改变TXWP值（S391）。如果不为空，则主板向奴隶板生成发送缓冲器满中断（S370）并等待处于空闲状态（S371）。如果主控板接收到缓冲区满终端中断（S380），则主控板重新开启消息传输。如果设置方法2，则主板读取传输缓冲器和读写指针并计算用于计算缓冲器满度的空缓冲器的数量（S350）。主板将设置的参考值与缓冲器充满度进行比较以判断缓冲器已满（S360）。

7. 发明授权

KR100311227B1 이중화로 구성된 셀 다중 장치 및 그를 이용한 이중화제어 방법 失效
标题翻译：重复单元复用的装置和使用它的重复控制的方法
公开(公告)号：KR100311227B1
公开(公告)日：2001-10-12
申请号：KR1019990062164
申请日：1999-12-24
申请人： 한국전자통신연구원 , 주식회사 케이티
发明人： 박만식 , 송광석
IPC分类号： H04L12/28
摘要： 본발명은비동기전송모드교환기에서프로세서간의통신을위해스위치와프로세서사이에접속되어다중통신포트를제공하는이중화로구성된셀 다중장치및 그를이용한이중화제어방법에관한것으로, 셀다중장치의통신경로제어정보에대해고도의신뢰성과안정성을확보하여연속적인시스템서비스를수행하기위한, 이중화로구성된셀 다중장치및 그를이용한이중화제어방법을제공하기위하여, 제1셀다중장치의셀 전송경로제어정보를관리하며상기셀 전송경로제어정보에대한변경요구가있는경우상기셀 전송경로제어정보를변경하기위한가상경로식별자저장수단; 외부교환기스위치링크로부터신호를전달받아상기가상경로식별자저장수단의상기셀 전송경로제어정보를이용하여각각의다중화된프로세서와통신을하기위한프로세서통신수단; 상기제1셀다중장치의상태변경요구및 이중화신호를감지하여상기전송경로제어정보의변경을제어하기위한이중화제어수단; 및상기이중화제어수단의제어를받아상기가상경로식별자저장수단으로부터변경된상기셀 전송경로제어정보를읽어와제2셀다중장치로전달하기위한이중포트저장수단을포함하며, 교환시스템등에이용됨.

8. 发明公开

KR1020010063096A 이중화된 데이터 채널을 갖는 동시 쓰기 방식을 적용한결함 허용 제어 시스템 失效
标题翻译：用于控制具有双数据通道的同时写入系统的故障许可证系统
公开(公告)号：KR1020010063096A
公开(公告)日：2001-07-09
申请号：KR1019990059970
申请日：1999-12-21
申请人： 한국전자통신연구원 , 주식회사 케이티
发明人： 정우석 , 송광석
IPC分类号： H04L12/40
摘要： PURPOSE: A system for controlling fault permission applying a simultaneous write system having dual data channels is provided to configure two data channels for the simultaneous write. Therefore, if a fault is generated in one channel, bypass to the other channel can be performed. CONSTITUTION: In an active processor module and a standby processor module, CPUs(10,11) control entire system. Input/output units(20,21) input/output data to the system. Memories(30,31) store programs, operation state information and date necessary for the operation of the system. Active data channels(40,41) form data channels for simultaneous write. Standby data channels(50,51) are for the simultaneous write, if a fault of a data channel formed by the active data channels(40,41) is generated.
摘要翻译：目的：提供一种用于控制应用具有双数据通道的同时写入系统的故障许可的系统，以配置用于同时写入的两个数据通道。因此，如果在一个通道中产生故障，则可以对其他通道进行旁路。构成：在有源处理器模块和备用处理器模块中，CPU（10,11）控制整个系统。输入/输出单元（20,21）输入/输出到系统的数据。记忆（30,31）存储程序，操作状态信息和系统操作所需的日期。活动数据通道（40,41）形成用于同时写入的数据通道。如果由活动数据信道（40,41）形成的数据信道的故障被产生，则待机数据信道（50,51）用于同时写入。

9. 发明公开

KR1020010016794A 비동기 전달 모드 셀 다중화 및 역다중화 장치 失效
标题翻译：用于多路复用和解复用ATM（异步传输模式）电池的设备
公开(公告)号：KR1020010016794A
公开(公告)日：2001-03-05
申请号：KR1019990031918
申请日：1999-08-04
申请人： 한국전자통신연구원 , 주식회사 케이티
发明人： 박만식 , 여환근 , 송광석
IPC分类号： H04L12/28
CPC分类号： H04L12/5601 , H04L2012/5652 , H04L2012/5672
摘要： PURPOSE: An apparatus for multiplexing and demultiplexing ATM(Asynchronous Transfer Mode) cells is provided to implement a hardware to generate the ATM cells according to an ATM switch cell structure, to transmit the ATM cells, and to disassemble message-unit data into cell units to assemble cell-unit data into message units, so as to reliably exchange many information in a shortest time. CONSTITUTION: Serial/parallel(S/P) converters(411-41N) convert serial cell data into parallel cell data. Transmission controllers(421-42N) store converted parallel cells in transmission FIFOs(First-In-First-Outs)(431-43N), and supply a cell storage completion signal indicating one cell storage completion. A local processor(441) generates ATM(Asynchronous Transfer Mode) cells to store the ATM cells in an FIFO(43(N+1)), and supplies the cell storage completion signal. A transmission FIFO controller(442) selectively transmits the parallel cells according to an FIFO selection signal, and supplies a cell transmission completion signal indicating a cell transmission completion. A cell counter(443) counts the number of cells transmitted to the transmission FIFOs(431-43N) from the transmission controllers(421-42N), and counts the number of cells transmitted to the transmission FIFO(43(N+1)) from the local processor(441), according to the cell storage completion signals. The cell counter(443) counts the number of cells transmitted from the transmission FIFOs(431-43N) through the transmission FIFO controller(442) according to the cell transmission completion signal, and outputs a FIFO request signal. An FIFO selection controller(444) inputs the FIFO request signal to output an FIFO selection signal for transmitting cells stored in one transmission FIFO of the transmission FIFOs(431-43N). A cell rearranger(445) rearranges the ATM cells stored in the transmission FIFOs(431-43N). A cell selector(446) selectively transmits the cells transmitted from the transmission FIFO controller(442) and the rearranged ATM cells to a cell interface(447), according to the FIFO selection signal.
摘要翻译：目的：提供ATM（异步传输模式）单元的复用和解复用装置，以实现硬件，根据ATM交换单元结构生成ATM信元，发送ATM信元，并将消息单元数据拆解成单元单元将单元格数据组合成消息单元，以便在最短时间内可靠地交换许多信息。构成：串行/并行（S / P）转换器（411-41N）将串行单元数据转换为并行单元数据。传输控制器（421-42N）将传输FIFO（先进先出）（431-43N））中的转换并行单元存储，并提供指示一个单元存储完成的单元存储完成信号。本地处理器（441）生成ATM（异步传输模式）单元以将ATM信元存储在FIFO（43（N + 1））中，并提供单元存储完成信号。发送FIFO控制器（442）根据FIFO选择信号选择性地发送并行小区，并提供指示小区传输完成的小区发送完成信号。单元计数器（443）对从发送控制器（421-42N）发送到发送FIFO（431-43N）的小区数进行计数，并且对发送到发送FIFO（43（N + 1））的小区数进行计数，从本地处理器（441），根据单元存储完成信号。单元计数器（443）根据单元传输完成信号对通过传输FIFO控制器（442）从传输FIFO（431-43N）发送的单元的数目进行计数，并输出FIFO请求信号。 FIFO选择控制器（444）输入FIFO请求信号以输出用于发送存储在传输FIFO（431-43N）的一个传输FIFO中的小区的FIFO选择信号。单元重排器（445）重新排列存储在传输FIFO（431-43N）中的ATM信元。小区选择器（446）根据FIFO选择信号选择性地将从传输FIFO控制器（442）发送的小区和重新排列的ATM信元发送到小区接口（447）。

10. 发明公开

KR1020000032681A 프로세서간통신메시지를이용한상태관리방법 失效
标题翻译：使用流程之间的通信信息管理状态的方法
公开(公告)号：KR1020000032681A
公开(公告)日：2000-06-15
申请号：KR1019980049232
申请日：1998-11-17
申请人： 주식회사 케이티 , 한국전자통신연구원
发明人： 박혜숙 , 박만식 , 여환근 , 송광석
IPC分类号： H04L12/58
摘要： PURPOSE: A method for managing state using communication message between processes is provided to decrease a loss of cells by performing a state report, a failure monitoring, and a failure recovery of a cell multiplexer and demultiplexer board assembly(CMDA). CONSTITUTION: It is tested as to whether an error is occurred when an interrupt for informing an obstacle/failure of a CMDA board(604,605). A firmware(52) re-operates the CMDA board to perform an initial work when the error is occurred(601). The firmware(52) performs a basic operation continuously when the error is occurred. A signal of a message is analyzed when a message receiving interrupt is generated from a upper processor(606,607). It is judged as to whether the CMDA board is reset when a board reset request signal is received from the upper processor(608). The CDMA board is operated and the firmware performs an initial work when the received board reset request signal is a reset command(601). A basic operation of the firmware is continuously performed when the received board reset request signal is the reset command(603).
摘要翻译：目的：提供一种在进程之间使用通信消息管理状态的方法，以通过执行信元多路复用器和解复用器板组件（CMDA）的状态报告，故障监视和故障恢复来减少信元的丢失。规定：对通知CMDA板的障碍物/故障的中断（604,605）是否发生错误进行了测试。当发生错误时，固件（52）重新操作CMDA板执行初始工作（601）。当发生错误时，固件（52）持续执行基本操作。当从上位处理器生成消息接收中断时，分析消息的信号（606,607）。当从上位处理器（608）接收到板复位请求信号时，判断CMDA板是否复位。当接收到的板重置请求信号是复位命令（601）时，操作CDMA板并且固件执行初始工作。当接收到的板重置请求信号是复位命令（603）时，持续执行固件的基本操作。

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