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1. 发明公开

KR1020010007600A 두꺼운 접합 산화물을 구비한 접합형 웨이퍼 상에 확산배면 층을 제조하는 방법 无效
标题翻译：用氧化铁薄膜制造粘结剂背面扩散层的方法
公开(公告)号：KR1020010007600A
公开(公告)日：2001-01-26
申请号：KR1020000036928
申请日：2000-06-30
申请人： 인터실 코포레이션
发明人： 차가스조셉 , 우드베리더스틴 , 비솜제임스
IPC分类号： H01L21/22
CPC分类号： H01L21/2253 , H01L21/187 , H01L21/2007 , H01L21/2255 , H01L21/2256 , H01L21/26513 , H01L21/74 , H01L21/76251 , H01L29/0615 , H01L29/10 , H01L29/1079 , H01L29/1083 , Y10S438/933
摘要： PURPOSE: A method for manufacturing diffusion backside layer of bond wafer with thick bond oxide is provided to manufacture the diffusion dope back oxide layer of a device wafer that is subjected to oxide connection to a handle wafer by utilizing the combination of a thermal bond oxide or a thermal and deposition oxide. CONSTITUTION: A handle wafer(20) with a p-type layer on a surface is diffused to the bottom part of a device wafer(10) via a bond oxide(14) during a wafer bond operation and a high-temperature cycle, thus forming a desired p-type bottom layer(12). The concentration of a p-type dopant being introduced into the bottom part of the device wafer(10) is adjusted by the thickness of a bottom separation oxide, the concentration of the p-type dopant, and the product of diffusion rate and time that composite structure receives. The bond oxide(14) grows into a p-type handle wafer(20) and introduces the p-type dopant to the oxide. The wafer has a 2 micrometer growth oxide and is connected to an n-type wafer. The p-type layer is formed on a wafer of that type.
摘要翻译：目的：提供一种用于制造具有厚粘结氧化物的接合晶片的扩散背面层的方法，以通过利用热粘合氧化物或热粘合氧化物的组合来制造器件晶片的扩散掺杂背面氧化物层，其经受氧化物连接到处理晶片热和沉积氧化物。构成：在晶片接合操作和高温循环期间，具有表面上的p型层的处理晶片（20）通过结合氧化物（14）扩散到器件晶片（10）的底部，因此形成所需的p型底层（12）。引入到器件晶片（10）的底部的p型掺杂剂的浓度通过底部分离氧化物的厚度，p型掺杂剂的浓度以及扩散速率和时间的乘积来调节复合结构接收。键合氧化物（14）生长成p型处理晶片（20）并将p型掺杂剂引入到氧化物中。晶片具有2微米的生长氧化物并且连接到n型晶片。 p型层形成在该类型的晶片上。

2. 发明公开

KR1020010007504A 집적된 저항 콘택 无效
标题翻译：集成电阻联系人
公开(公告)号：KR1020010007504A
公开(公告)日：2001-01-26
申请号：KR1020000034785
申请日：2000-06-23
申请人： 인터실 코포레이션
发明人： 우드베리더스틴 , 차가스조셉
IPC分类号： H01L27/00
CPC分类号： H01L28/20 , H01L21/28512 , H01L21/28518 , Y10S257/914
摘要： PURPOSE: An integrated resistance contact is provided to eliminate the need for incorporating an added resistance layer by changing a desired silicon base material in contact to a material with desired high resistivity. CONSTITUTION: In a semiconductor device or an integrated circuit having a high resistance contact(10) and a low resistance contact(11), mobility spoiling species such as carbon or oxygen are implanted into all contacts. The high resistance contact(10) is coated with barrier metal(45), and silicide(35) is protected from chemical interaction with an interconnect metal(40) in the low resistance contact(11). The barrier metal(45) is usually masked by the interconnect metal(40) when etching. Although mobility spoiling implant is consumed by the silicide(35) at the low resistance contact(11) on the left, it remains undisturbed in the high resistance contact(10) on the right. Therefore, the low resistance contact(11) can be differentiated from the high resistance contact(10) without requiring deposition of an added resistive layer, and without using an added circuit surface area in less processes than those associated with high temperature annealing.
摘要翻译：目的：提供集成的电阻接触，以消除通过将期望的硅基材料与具有期望的高电阻率的材料接触来改变掺入添加的电阻层的需要。构成：在具有高电阻触点（10）和低电阻触点（11）的半导体器件或集成电路中，将移动性破坏物质例如碳或氧注入所有触点中。高电阻触点（10）涂覆有阻挡金属（45），并且防止硅化物（35）与低电阻触点（11）中的互连金属（40）的化学相互作用。当蚀刻时，阻挡金属（45）通常被互连金属（40）掩蔽。尽管在左侧的低电阻触点（11），由硅化物（35）消耗移动性损坏注入，但是它在右侧的高电阻触点（10）中保持不受干扰。因此，低电阻触点（11）可以与高电阻触点（10）不同，而不需要附加电阻层的沉积，并且不需要比与高温退火相关的工艺更少的工艺中使用添加的电路表面积。

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