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    • 2. 发明公开
    • 집적 회로 테스트를 위한 저전력 및 영역 효율적인 스캔 셀
    • 用于集成电路测试的低功耗和区域高效扫描电路
    • KR1020120108910A
    • 2012-10-05
    • KR1020110132930
    • 2011-12-12
    • 엘에스아이 코포레이션
    • 테쿠말라라메쉬씨쿠마르프리예쉬크리쉬나무어시프라카쉬마다니파라그
    • G01R31/28
    • G01R31/318541G01R31/318575
    • PURPOSE: A low power and domain efficient scan cell for an integrated circuit test is provided to reduce power consumption of an integrated circuit. CONSTITUTION: A scan test circuit comprises one or more scan-chains(204-k) having a plurality of scan-cells. The scan-chain is driven as a serial shift resister in a scan shift operation mode and captures functional data from one portion of an additional circuit in a function operation mode. A specific scan cell of the scan-chain comprises an output control circuit. The output control circuit rules out the use of functional data output of the plurality of scan-cells in the scan shift operation mode. The output control circuit rules out the use of scan output of the plurality of scan-cells in the function operation mode. [Reference numerals] (200) Decompression device; (202) Compressor; (207) Circuit under test; (208,201,212) Matrix logic; (AA,BB,CC,DD,EE,FF) Cell; (GG,HH) Scan chain
    • 目的:提供用于集成电路测试的低功率和有效域扫描单元,以降低集成电路的功耗。 构成:扫描测试电路包括具有多个扫描单元的一个或多个扫描链(204-k)。 扫描链在扫描移位操作模式中被驱动为串行移位寄存器,并且在功能操作模式中从附加电路的一部分捕获功能数据。 扫描链的特定扫描单元包括输出控制电路。 输出控制电路在扫描移位操作模式中排除了使用多个扫描单元的功能数据输出。 输出控制电路在功能运行模式中排除了多个扫描单元的扫描输出的使用。 (附图标记)(200)减压装置; (202)压缩机; (207)被测电路; (208,201,212)矩阵逻辑; (AA,BB,CC,DD,EE,FF)Cell; (GG,HH)扫描链