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    • 3. 发明授权
    • 강유전체 기억소자의 셀 구조
    • 강유전체기억소자의셀구조
    • KR100363104B1
    • 2003-02-19
    • KR1019980045566
    • 1998-10-28
    • 에스케이하이닉스 주식회사
    • 김덕주박재훈
    • G11C11/22
    • G11C11/22
    • The present invention relates to a cell structure of a ferroelectric memory device which can prevent a data loss and improve a data read/write speed, including: first and second MOS transistors connected in series between two bit lines, and performing a switching operation according to an enable state of a word line; a third MOS transistor connected between the first and second MOS transistors and a plate line, and engaged with the first and second MOS transistors according to an enable state the word line; and first and second ferroelectric capacitors connected between the first MOS transistor and the third MOS transistor, and between the second MOS transistor and the third MOS transistor, respectively, and storing data in accordance with a switching state of the first to third MOS transistors. Accordingly, the present invention can carry out a high-speed data sensing operation and a restoring operation, and can prevent the data from being lost, which results in improved speed and reliability.
    • 本发明涉及可防止数据丢失并提高数据读写速度的铁电存储器件的单元结构,包括:串联连接在两条位线之间的第一和第二MOS晶体管,并根据 字线的使能状态; 第三MOS晶体管,连接在第一MOS晶体管和第二MOS晶体管与板线之间,并且根据字线的使能状态与第一MOS晶体管和第二MOS晶体管接合; 以及分别连接在第一MOS晶体管和第三MOS晶体管之间以及第二MOS晶体管和第三MOS晶体管之间并根据第一到第三MOS晶体管的开关状态存储数据的第一和第二铁电电容器。 因此,本发明可以执行高速数据读出操作和恢复操作,并且可以防止数据丢失,这导致提高的速度和可靠性。
    • 4. 发明公开
    • 강유전체 기억소자의 셀 구조
    • 电解记忆体细胞结构
    • KR1020000027611A
    • 2000-05-15
    • KR1019980045566
    • 1998-10-28
    • 에스케이하이닉스 주식회사
    • 김덕주박재훈
    • G11C11/22
    • G11C11/22
    • PURPOSE: A cell structure for ferroelectric memory cell is provided to improve a velocity and a reliability by performing a high data sensing operation and a re-storing operation to prevent a data loss. CONSTITUTION: First and second MOS transistors(N0,N1) are interconnected in serial between two bit lines(BL0,BL1). Gates of first and second MOS transistor(N0,N1) are connected to a word line(WL). A third MOS transistor(N3) is connected between first and second MOS transistors(N0,N1) and plate lines(PL). Gate of the third MOS transistor(N3) is connected to the word line(WL). A source of the first MOS transistor(N0) is connected to a upper electrode of a first ferroelectric capacitor(X0). A source of the second MOS transistor(N1) is connected to a upper electrode of a second ferroelectric capacitor(X1). Lower electrodes of the first ferroelectric capacitor(X0) and the second ferroelectric capacitor(X1) are interconnected and connected to a drain of the third MOS transistor(N3). A source of the third MOS transistor(N3) is connected to the plate line(PL).
    • 目的:提供铁电存储器单元的单元结构,通过执行高数据检测操作和重新存储操作以防止数据丢失来提高速度和可靠性。 构成:第一和第二MOS晶体管(N0,N1)串联连接在两个位线(BL0,BL1)之间。 第一和第二MOS晶体管(N0,N1)的栅极连接到字线(WL)。 第三MOS晶体管(N3)连接在第一和第二MOS晶体管(N0,N1)和板极线(PL)之间。 第三MOS晶体管(N3)的栅极连接到字线(WL)。 第一MOS晶体管(N0)的源极连接到第一铁电电容器(X0)的上电极。 第二MOS晶体管(N1)的源极连接到第二铁电电容器(X1)的上电极。 第一铁电电容器(X0)和第二铁电电容器(X1)的下电极互连并连接到第三MOS晶体管(N3)的漏极。 第三MOS晶体管(N3)的源极连接到板线(PL)。