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1. 发明公开

KR1020170074727A 집적 회로 审中-实审
标题翻译：集成电路
公开(公告)号：KR1020170074727A
公开(公告)日：2017-06-30
申请号：KR1020160021132
申请日：2016-02-23
申请人： 에스케이하이닉스 주식회사
发明人： 김재헌
IPC分类号： G11C5/14 , H03K3/011 , G11C7/06 , G11C7/10 , G05F3/20
摘要： 집적회로는, 바이어스전류를생성하는전류바이어스생성기; 상기바이어스전류를미러링한제1바이어스전류에의해바이어싱되어동작하고, 상기바이어스전류를미러링한제2바이어스전류를생성하는제1회로; 및상기제2바이어스전류를미러링한제3바이어스전류에의해바이어싱되어동작하고, 상기제2바이어스전류를미러링한제4바이어스전류를생성하는제2회로를포함할수 있다.
摘要翻译：该集成电路包括：用于产生偏置电流的电流偏置发生器; 第一电路，通过被偏置电流镜像化的第一偏置电流偏置并产生与偏置电流镜像的第二偏置电流来操作; 以及通过被第三偏置电流偏置而工作的第二电路，所述第三偏置电流镜像所述第二偏置电流并产生镜像所述第二偏置电流的第四偏置电流。

2. 发明公开

KR1020120126725A 반도체 소자의 형성 방법 无效
标题翻译：半导体器件形成方法
公开(公告)号：KR1020120126725A
公开(公告)日：2012-11-21
申请号：KR1020110044743
申请日：2011-05-12
申请人： 에스케이하이닉스 주식회사
发明人： 김재헌 , 복철규
IPC分类号： H01L21/027 , H01L21/28
CPC分类号： H01L21/31144 , B81C1/00031 , B81C2201/0149 , H01L21/0337 , H01L21/0274
摘要： PURPOSE: A formation method of a semiconductor device is provided to improve yield of the semiconductor device by improving non-uniformity of a contact hole pattern while reducing an interval between contact holes of the semiconductor device. CONSTITUTION: An amorphous carbon layer(102) and a polysilicon layer(104) are formed on a semiconductor substrate(100). A photosensitive pattern(108) is formed on the upper side of the polysilicon layer. A block copolymer which includes polymer(110b) having a hydrophobic group and polymer(110a) having a hydrophilic group is formed between photosensitive patterns. The block copolymer is arranged inside the polymer having the hydrophilic group. The polymer having the hydrophobic group is selectively eliminated.
摘要翻译：目的：提供半导体器件的形成方法，以通过改善接触孔图案的不均匀性同时减小半导体器件的接触孔之间的间隔来提高半导体器件的产量。构成：在半导体衬底（100）上形成无定形碳层（102）和多晶硅层（104）。在多晶硅层的上侧形成有感光图案（108）。在感光图案之间形成包含具有疏水基团的聚合物（110b）和具有亲水基团的聚合物（110a）的嵌段共聚物。嵌段共聚物布置在具有亲水基团的聚合物的内部。选择性地除去具有疏水基团的聚合物。

3. 发明授权

KR101002526B1 플래시 메모리 소자 및 그 제조 방법 失效
标题翻译：闪存装置及其制造方法
公开(公告)号：KR101002526B1
公开(公告)日：2010-12-17
申请号：KR1020080081740
申请日：2008-08-21
申请人： 에스케이하이닉스 주식회사
发明人： 김재헌
IPC分类号： H01L27/115 , H01L21/28 , H01L21/8247
CPC分类号： H01L27/11521 , H01L21/76807 , H01L21/76831 , H01L21/76895 , H01L21/76897 , H01L27/11519
摘要： 본 발명은 플래시 메모리 소자 및 그 제조 방법에 관한 것으로, 특히 콘택 플러그 형성 시 콘택 플러그들 중 이븐(even) 또는 오드(odd) 그룹에 속하는 콘택 플러그들을 형성한 후 패드 콘택 플러그들을 형성한 다음, 콘택 플러그들 중 나머지 그룹에 속하는 콘택 플러그들을 형성하는 콘택 형성 스킴(scheme)을 적용하여 교호적으로 서로 다른 높이의 콘택 플러그를 형성함으로써, 콘택 플러그 간 브릿지 발생을 방지함과 동시에 콘택 플러그의 매립 특성을 향상시킬 수 있는 플래시 메모리 소자 및 그 제조 방법에 관한 것이다.
플래시 메모리, 드레인 콘택홀, 드레인 콘택 플러그, 브릿지, 보이드
摘要翻译：本发明是一种快闪存储器装置并且涉及制造方法，特别是一种方法，在形成接触插塞属于在地层IBN（偶数）或奇数（奇数）组的接触插塞的接触插塞中的一个，以形成垫接触插塞以后，然后，接触通过采用接触形成方案交替地形成不同高度的接触塞来形成属于其余组塞的接触塞，可以防止接触塞之间发生桥接，及其制造方法。

4. 发明公开

KR1020100023132A 플래시 메모리 소자 및 그 제조 방법 失效
标题翻译：闪存存储器件及其制造方法
公开(公告)号：KR1020100023132A
公开(公告)日：2010-03-04
申请号：KR1020080081740
申请日：2008-08-21
申请人： 에스케이하이닉스 주식회사
发明人： 김재헌
IPC分类号： H01L27/115 , H01L21/28 , H01L21/8247
CPC分类号： H01L27/11521 , H01L21/76807 , H01L21/76831 , H01L21/76895 , H01L21/76897 , H01L27/11519 , H01L21/28141
摘要： PURPOSE: A flash memory device and a manufacturing method thereof are provided to prevent a bridge between a contact plugs by forming a even group contact plug, a pad contact plug, and an odd group contact plug. CONSTITUTION: A flash memory device comprises a first contact plug(124a), a second contact plug(124b), a first and second conductive pads(130a,130b), a first and second pad contact plugs(138a,138b), and a first bit line(BL1) and a second bit line(BL2). The first contact plugs are formed on the semiconductor substrate(100). The second contact plugs is higher than first contact plugs. The first and second conductive pads are connected to the first contact plug. The first bit lines are connected to the first and second pad contact plugs. The second bit lines are connected to the second contact plugs.
摘要翻译：目的：提供闪存器件及其制造方法，以通过形成偶数组接触插塞，焊盘接触插头和奇数组接触插头来防止接触插塞之间的桥接。构成：闪速存储器件包括第一接触插塞（124a），第二接触插塞（124b），第一和第二导电焊盘（130a，130b），第一和第二焊盘接触插塞（138a，138b）和第一位线（BL1）和第二位线（BL2）。第一接触插塞形成在半导体衬底（100）上。第二接触塞比第一接触塞高。第一和第二导电焊盘连接到第一接触插头。第一位线连接到第一和第二焊盘接触插头。第二位线连接到第二接触插头。

5. 发明公开

KR1020090072087A 반도체 소자의 소자 분리막 형성 방법 无效
标题翻译：形成半导体器件隔离膜的方法
公开(公告)号：KR1020090072087A
公开(公告)日：2009-07-02
申请号：KR1020070140079
申请日：2007-12-28
申请人： 에스케이하이닉스 주식회사
发明人： 김재헌
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L29/66825
摘要： A method for forming an isolation film of a semiconductor device is provided to prevent generation of a void inside an isolation film by securing depth of a trench through additional etching of a low surface of a trench. A trench(105) for isolating a device having a fixed side wall slope is formed by etching an isolation region of a semiconductor substrate(100). A liner insulation film(106A) is formed on a side wall of the trench for isolating the device. A depth of the trench for isolating the device is increased by etching a low surface of the trench for isolating the device. An isolation film is formed by filling the trench for isolating the device with an insulation film. A tunnel insulation film(101) and a charge storage layer(102) are formed on the semiconductor substrate. A depth of the trench for isolating the device is increased by etching the low surface of the trench for isolating the device.
摘要翻译：提供了形成半导体器件的隔离膜的方法，以通过通过对沟槽的低表面进行另外的蚀刻来确保沟槽的深度来防止在隔离膜内产生空隙。通过蚀刻半导体衬底（100）的隔离区域，形成用于隔离具有固定侧壁斜面的器件的沟槽（105）。衬垫绝缘膜（106A）形成在沟槽的侧壁上，用于隔离该装置。用于隔离器件的沟槽的深度通过蚀刻用于隔离器件的沟槽的低表面而增加。通过用绝缘膜填充用于隔离该器件的沟槽来形成隔离膜。在半导体衬底上形成隧道绝缘膜（101）和电荷存储层（102）。用于隔离器件的沟槽的深度通过蚀刻用于隔离器件的沟槽的低表面而增加。

6. 发明公开

KR1020080090970A 플래시 메모리 소자의 제조 방법 失效
标题翻译：制造闪速存储器件的方法
公开(公告)号：KR1020080090970A
公开(公告)日：2008-10-09
申请号：KR1020080015341
申请日：2008-02-20
申请人： 에스케이하이닉스 주식회사
发明人： 김재헌
IPC分类号： H01L27/115 , H01L21/28
CPC分类号： H01L21/76838 , H01L21/28273 , H01L21/76224 , H01L21/76256 , H01L21/76877
摘要： A method for manufacturing a flash memory device is provided to improve the bridge margin between contact holes to prevent bridge from being generated between adjacent drain contact plugs by effectively eliminating a bowing shape in a CMP process after exposing the bowing shape occurring in forming a contact hole. A method for manufacturing a flash memory device comprises the following steps of: forming an interlayer insulation layer(108) on a semiconductor substrate(100); etching the interlayer insulation layer to form a first contact hole(110) exposing an adhesion region of a cell region; forming a first contact plug in the first contact hole; etching an upper portion of the interlayer insulation layer to expose the greatest width part of the first contact plug; etching the interlayer insulation layer to form a second contact hole(116) exposing an adhesion region of a peripheral circuit region; forming a second metal layer on the first contact plug and the interlayer insulation layer filling the second contact hole; and etching the second metal layer in the upper portion of the interlayer insulation layer and an exposed part of the first contact plug to form a second contact plug in the second contact hole.
摘要翻译：提供了一种用于制造闪速存储器件的方法，以改善接触孔之间的桥接裕度，以防止在形成接触孔中发生的弯曲形状之后通过有效地消除CMP工艺中的弓形而在相邻的漏极接触插塞之间产生桥接。一种制造闪存器件的方法包括以下步骤：在半导体衬底（100）上形成层间绝缘层（108）; 蚀刻层间绝缘层以形成暴露单元区域的粘附区域的第一接触孔（110）; 在所述第一接触孔中形成第一接触插塞; 蚀刻层间绝缘层的上部以露出第一接触插塞的最大宽度部分; 蚀刻层间绝缘层以形成露出外围电路区域的粘附区域的第二接触孔（116）; 在第一接触插塞和填充第二接触孔的层间绝缘层上形成第二金属层; 并且蚀刻层间绝缘层的上部中的第二金属层和第一接触插塞的暴露部分，以在第二接触孔中形成第二接触插塞。

7. 发明公开

KR1020080078997A 반도체 소자의 금속 배선 형성 방법 无效
标题翻译：在半导体器件中形成金属线的方法
公开(公告)号：KR1020080078997A
公开(公告)日：2008-08-29
申请号：KR1020070018970
申请日：2007-02-26
申请人： 에스케이하이닉스 주식회사
发明人： 김재헌
IPC分类号： H01L21/28 , H01L21/283
摘要： A method of forming a metal wire in a semiconductor device is provided to prevent damage of a second insulating layer by forming a spacer at a side wall of the second insulating layer using a PE-nitride layer. A semiconductor substrate(100) having a first insulating layer with contact plugs(108) is prepared. An etch stop layer(110) and a second insulating layer(112) are formed on the semiconductor substrate having the first insulating layer and the contact plugs. By etching the second insulating layer and the etch stop layer, a trench for exposing the contact plugs is formed. A third insulating layer is formed on the semiconductor substrate having the trench using a PE(Plasma Enhanced)-CVD scheme. By etching the third insulating layer, a spacer(122) is formed at a side wall of the trench. A metal line(126) is formed in the trench.
摘要翻译：提供一种在半导体器件中形成金属线的方法，以通过在第二绝缘层的侧壁上使用PE-氮化物层形成间隔物来防止第二绝缘层的损坏。制备具有带有接触塞（108）的第一绝缘层的半导体衬底（100）。在具有第一绝缘层和接触插塞的半导体衬底上形成蚀刻停止层（110）和第二绝缘层（112）。通过蚀刻第二绝缘层和蚀刻停止层，形成用于暴露接触插塞的沟槽。使用PE（等离子增强）-CVD方案在具有沟槽的半导体衬底上形成第三绝缘层。通过蚀刻第三绝缘层，在沟槽的侧壁处形成间隔物（122）。在沟槽中形成金属线（126）。

8. 发明公开

KR1020070059324A ＮＡＮＤ형 플래쉬 메모리 소자의 제조 방법 无效
标题翻译：制造NAND型闪存存储器件的方法
公开(公告)号：KR1020070059324A
公开(公告)日：2007-06-12
申请号：KR1020050118037
申请日：2005-12-06
申请人： 에스케이하이닉스 주식회사
发明人： 김재헌
IPC分类号： H01L21/8247 , H01L27/115
摘要： A method for fabricating a NAND-type flash memory device is provided to minimize the possibility of damaging a SAC(self-align contact) in an etch process for forming a contact by forming a gate spacer nitride layer after a gate buffer oxide layer in a contact formation region is selectively removed by an etch process. After a gate in which a tunnel oxide layer(102), a plurality of conductive layers and a hard mask layer(112) are stacked is formed in a predetermined region on a semiconductor substrate(100), a selective oxide process is performed on the sidewall of the gate. A junction region(116) is formed on the semiconductor substrate between the gates. After a buffer oxide layer(118) is formed on the resultant structure, a part of the buffer oxide layer formed on a contact hole formation region and the hard mask layer are removed by a selective wet-etch process using chemical made of NH4F and HF. A spacer nitride layer(122), an SAC buffer oxide layer(124), an SAC nitride layer(126), a first interlayer dielectric and a second interlayer dielectric(130) are sequentially formed on the resultant structure. An etch process for forming a self-align contact is performed to form a contact hole, and the SAC nitride layer, the SAC buffer oxide layer and the spacer nitride layer in the lower part of the contact hole are removed to expose the junction part. A conductive material is filled in the contact hole to form a contact plug(134).
摘要翻译：提供了一种用于制造NAND型闪速存储器件的方法，以最小化在用于形成接触的蚀刻工艺中损害SAC（自对准接触）的可能性，以便在栅极间隔层氮化物层之后形成栅极间隔层氮化物层通过蚀刻工艺选择性地去除接触形成区域。在半导体衬底（100）上的预定区域中形成隧道氧化物层（102），多个导电层和硬掩模层（112）的栅极之后，对其进行选择性氧化处理门的侧壁。在栅极之间的半导体衬底上形成结区域（116）。在所得结构上形成缓冲氧化物层（118）之后，通过使用由NH 4 F和HF制成的化学物质的选择性湿蚀刻工艺除去形成在接触孔形成区域上的缓冲氧化物层的一部分和硬掩模层。在所得结构上依次形成间隔氮化物层（122），SAC缓冲氧化物层（124），SAC氮化物层（126），第一层间电介质和第二层间电介质（130）。进行用于形成自对准接触的蚀刻工艺以形成接触孔，并且去除接触孔下部中的SAC氮化物层，SAC缓冲氧化物层和间隔氮化物层以暴露接合部分。导电材料填充在接触孔中以形成接触塞（134）。

9. 发明授权

KR100607348B1 반도체 소자의 금속 배선 형성 방법 失效
标题翻译：在半导体器件中形成金属线的方法
公开(公告)号：KR100607348B1
公开(公告)日：2006-07-28
申请号：KR1020040072498
申请日：2004-09-10
申请人： 에스케이하이닉스 주식회사
发明人： 김재헌
IPC分类号： H01L21/28
摘要： 본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 단차가 서로 다른 반도체 기판, 게이트 및 소오스 콘택 플러그를 노출시키는 콘택 및 트렌치를 형성한 후 도전층을 매립하여 금속 배선을 형성하는 공정에서 게이트 상부에 하드 마스크막을 산화막으로 형성하고, 반도체 기판을 노출시키는 콘택 마스크와 게이트를 노출시키는 콘택 마스크를 분리하지 않고 자기정렬 콘택(SAC) 식각 공정을 실시한 후 트렌치를 형성함으로써 반도체 기판의 손상을 조절하여 저항 증가 및 불균일을 해결할 수 있는 반도체 소자의 금속 배선 형성 방법이 제시된다.
금속 배선, SAC, 콘택 퍼스트, 콘택 마스크

10. 发明授权

KR100415088B1 반도체장치의 제조방법 失效
标题翻译： 반도체장치의제조방법
公开(公告)号：KR100415088B1
公开(公告)日：2004-01-13
申请号：KR1020010063309
申请日：2001-10-15
申请人： 에스케이하이닉스 주식회사
发明人： 조성윤 , 김재헌
IPC分类号： H01L21/28
CPC分类号： H01L21/31144 , H01L21/31138 , H01L21/76816
摘要： A method for fabricating a semiconductor device capable of maintaining contact hole of fine size when the contact hole for bit line formation is defined. The method comprises the steps of: sequentially forming an insulating layer and an Anti-Reflective Coating layer on a substrate, the substrate including conductive regions; forming a photoresist pattern opening in the Anti-Reflective Coating layer over the conductive regions; removing the Anti-Reflective Coating layer in accordance with a first dry etch process using a mixed gas of SO2 and He and employing the photoresist pattern as an etch mask and at the same time, attaching polymers resulting from the dry etch process to the side of remaining Anti-Reflective Coating layer, thereby forming a polymer sidewall; removing the insulating layer in accordance with a second dry etch process employing the photoresist pattern and the polymer sidewall as an etch mask, thereby forming a contact hole; and removing the photoresist pattern, the remaining Anti-Reflective Coating layer and the polymer sidewall.
摘要翻译：一种用于制造半导体器件的方法，当确定用于位线形成的接触孔时，该半导体器件能够保持精细尺寸的接触孔。该方法包括以下步骤：在衬底上顺序形成绝缘层和抗反射涂层，该衬底包括导电区域; 在导电区域上方的抗反射涂层中形成光致抗蚀剂图案开口; 根据使用SO 2和He的混合气体的第一干蚀刻工艺去除抗反射涂层，并且使用该光致抗蚀剂图案作为蚀刻掩模，并且同时将由干法蚀刻工艺产生的聚合物附着到剩余的抗反射涂层，由此形成聚合物侧壁; 根据采用光致抗蚀剂图案和聚合物侧壁作为蚀刻掩模的第二干蚀刻工艺去除绝缘层，由此形成接触孔; 并去除光致抗蚀剂图案，剩余的抗反射涂层和聚合物侧壁。

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