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1. 发明授权

KR102169668B1 무선통신 시스템에서 고주파처리 모듈 제어 방법 및 장치 有权
公开(公告)号：KR102169668B1
公开(公告)日：2020-10-23
申请号：KR1020140000772
申请日：2014-01-03
申请人： 삼성전자주식회사
发明人： 김찬영
IPC分类号： H04L25/02 , H04L29/10

2. 发明公开

KR1020140102849A 다중 무선 접속 기술 환경에서 사업자 네트워크 탐색 방법 및 장치 审中-实审
标题翻译：多种无线电接入技术环境中搜索操作员网络的方法和设备
公开(公告)号：KR1020140102849A
公开(公告)日：2014-08-25
申请号：KR1020130016227
申请日：2013-02-15
申请人： 삼성전자주식회사
发明人： 신청호 , 김찬영 , 배병재 , 송재호 , 허운행
IPC分类号： H04W48/16
CPC分类号： H04W48/16
摘要： A method and apparatus of searching for an operator network in a multi-radio access technology (RAT) environment are disclosed. The method comprises the following steps: calculating a length of a sleep period to perform background public land mobile network (PLMN) searching; comparing the length of the sleep period with a predetermined reference parameter; performing background PLMN searching of a passive RAT during the sleep period if the length of the sleep period is greater than the reference parameter; and performing background PLMN searching of an active RAT during the sleep period if the length of the sleep period is equal to or less than the reference parameter. The reference parameter may be determined taking into account a minimum time required for RAT switching in a user terminal or determined as a length of a previous sleep period.
摘要翻译：公开了一种在多无线电接入技术（RAT）环境中搜索运营商网络的方法和装置。该方法包括以下步骤：计算进行背景公共陆地移动网（PLMN）搜索的睡眠周期的长度; 将睡眠周期的长度与预定的参考参数进行比较; 如果睡眠周期的长度大于参考参数，则在休眠期间执行无源RAT的背景PLMN搜索; 以及如果所述睡眠周期的长度等于或小于所述参考参数，则在所述睡眠周期期间执行所述活动RAT的背景PLMN搜索。参考参数可以考虑用户终端中的RAT切换所需的最小时间或者确定为先前睡眠周期的长度来确定。

3. 发明公开

KR1020080010164A 안정적 동작을 위한 전류 감지 증폭기 无效
标题翻译：用于稳定运行的电流检测放大器电路
公开(公告)号：KR1020080010164A
公开(公告)日：2008-01-30
申请号：KR1020060070299
申请日：2006-07-26
申请人： 삼성전자주식회사
发明人： 김찬영 , 임준희
IPC分类号： G11C7/06 , G11C7/08
摘要： A current sense amplifier is provided to perform stable operation by transmitting data efficiently without increasing data transmission time by controlling CSA output gain. According to a current sense amplifier, a pair of data lines include a first and a second data line(IO,IOB). A sensing part(310) senses difference between two currents inputted through the first and the second data line, and outputs an output voltage of the first and the second data line by converting the current difference into voltage difference. An equalizing part(330) is connected between the first and the second data lines, and equalizes the first and the second data lines during disable state of a sensing start signal. A gain control part(350) is connected between the first and the second data lines, and restricts output voltage difference of the first and the second data line within a constant value. An output part(370) outputs the output voltage as being connected between the first and the second data lines, and outputs a current flowing through the first and the second data line to a ground voltage.
摘要翻译：通过控制CSA输出增益，提供电流检测放大器以通过有效传输数据而不增加数据传输时间来执行稳定的操作。根据电流检测放大器，一对数据线包括第一和第二数据线（IO，IOB）。感测部（310）感测通过第一和第二数据线输入的两个电流之间的差异，并且通过将电流差转换为电压差来输出第一和第二数据线的输出电压。均衡部分（330）连接在第一和第二数据线之间，并且在感测开始信号的禁用状态期间使第一和第二数据线均衡。增益控制部分（350）连接在第一和第二数据线之间，并将第一和第二数据线的输出电压差限制在恒定值内。输出部分（370）输出连接在第一和第二数据线之间的输出电压，并将流过第一和第二数据线的电流输出到接地电压。

4. 发明授权

KR100791076B1 전계 경감 트랜지스터를 구비한 로직 회로 및 이를 구비한반도체 장치 失效
标题翻译：包含场弛豫晶体管的逻辑电路和包含其的半导体器件
公开(公告)号：KR100791076B1
公开(公告)日：2008-01-03
申请号：KR1020060121571
申请日：2006-12-04
申请人： 삼성전자주식회사
发明人： 김찬영 , 임준희 , 김두영 , 김준형
IPC分类号： H01L21/335
CPC分类号： H03K19/018521 , H03K5/1534
摘要： A logic circuit comprising a field relaxation transistor and a semiconductor device comprising the same are provided to prevent deterioration of the field relaxation transistor and to prevent operation errors by applying a high voltage only in a short period of time according to a state of an input signal. A first transistor is connected between terminals for outputting a first voltage and an output signal and includes a gate for receiving an input signal. A second transistor is connected to a grounding voltage and includes a gate for receiving the input signal. A control unit(30) outputs a control signal which has a first voltage level in an input signal state changing section and a second voltage level in an input signal state unchanging section in response to the input signal. The second voltage level is lower than the first voltage level. A field relaxation transistor is connected between an output terminal and the second transistor and includes a gate for receiving the control signal.
摘要翻译：提供了包括场弛豫晶体管和包括该场稳定晶体管的半导体器件的逻辑电路，以防止场弛豫晶体管的劣化，并且仅根据输入信号的状态在短时间内施加高电压来防止操作错误。第一晶体管连接在用于输出第一电压和输出信号的端子之间，并且包括用于接收输入信号的栅极。第二晶体管连接到接地电压并且包括用于接收输入信号的栅极。控制单元（30）响应于输入信号，输出在输入信号状态改变部分具有第一电压电平的控制信号和输入信号状态不变部分中的第二电压电平。第二电压电平低于第一电压电平。场致松晶体管连接在输出端和第二晶体管之间，并包括用于接收控制信号的栅极。

5. 发明公开

KR1020050078435A 반도체 메모리 장치 및 이 장치의 셀프 리플레쉬 제어방법 无效
标题翻译：半导体存储器件及其自刷式控制方法
公开(公告)号：KR1020050078435A
公开(公告)日：2005-08-05
申请号：KR1020040005865
申请日：2004-01-29
申请人： 삼성전자주식회사
发明人： 김찬영 , 고태영
IPC分类号： G11C11/406
摘要： 본 발명은 반도체 메모리 장치 및 이 장치의 셀프 리플레쉬 제어방법을 공개한다. 그 장치는 리플레쉬 중지명령에 응답하여 리플레쉬 주기를 결정하는 카운터신호를 출력하는 스위치부, 상기 스위치부의 출력신호를 저장하고 출력하는 래치부, 상기 래치부의 출력신호에 응답하여 리플레쉬 동작을 수행하도록 하는 리플레쉬 마스터 신호를 발생하는 리플레쉬 마스터 신호 발생부, 상기 리플레쉬 마스터 신호가 비활성 상태인 때 상기 리플레쉬 중지명령보다 소정시간 앞선 프리차아지 제어신호에 응답하여 프리차아지 신호를 발생하는 프리차아지 제어부, 및 상기 프리차아지 신호에 응답하여 상기 래치부로 입력되는 신호를 소정 레벨로 만들어주는 프리차아지부로 구성된다. 따라서, 리플레쉬 주기를 결정하는 카운터 신호와 리플레쉬 중지명령이 동시에 인가될 경우, 리플레쉬 동작을 수행하도록 하는 리플레쉬 마스터 신호가 지연되어 발생함으로써 일어날 수 있는 오동작을 방지할 수 있다.

6. 发明公开

KR1020170142407A 단말간 직접 통신을 수행하는 통신 장치 및 그 동작 방법 审中-实审
标题翻译：用于执行终端之间的直接通信的通信装置及其操作方法
公开(公告)号：KR1020170142407A
公开(公告)日：2017-12-28
申请号：KR1020160075829
申请日：2016-06-17
申请人： 삼성전자주식회사
发明人： 박권열 , 김찬영 , 이상현
IPC分类号： H04W48/18 , H04W24/08 , H04W76/02 , H04W72/04 , H04W88/06
CPC分类号： H04W76/023 , H04W72/04 , H04W76/14 , H04W48/18 , H04W24/08 , H04W72/042 , H04W88/06
摘要： 단말간직접통신을수행하는통신장치및 그동작방법이개시된다. 본개시의기술적사상의일측면에따른통신장치의동작방법은, 기지국으로부터단말간직접(D2D) 통신을위한직접링크의자원을포함하는제1 메시지를수신하는단계와, D2D 통신의상대단말로부터제1 정보를포함하는제2 메시지를수신하는단계및 셀룰러통신의상향링크의채널정보와상기수신된제1 정보에기반하여, 상기셀룰러통신및 상기 D2D 통신중 어느하나를상기상대단말과의통신모드로서선택하는단계를구비하고, 상기제1 정보는상기셀룰러통신의하향링크의채널정보및 상기직접링크의채널정보에관련된것을특징으로한다.
摘要翻译：公开了一种用于执行终端之间的直接通信的通信装置及其操作方法。根据本公开的一方面，提供了一种操作通信设备的方法，所述方法包括：从基站接收包括用于直接（D2D）通信的直接链路资源的第一消息; 基于蜂窝通信或与对方终端的D2D通信，接收包括蜂窝通信的上行链路的第一信息和信道信息以及第一信息的第二消息 Mode，第一信息与蜂窝通信的下行信道信息和直接链路的信道信息有关。

7. 发明公开

KR1020070066501A 메모리 장치의 데이터 오더링 및 데이터 구성 방법 无效
标题翻译：存储器件的数据订购和组织方法
公开(公告)号：KR1020070066501A
公开(公告)日：2007-06-27
申请号：KR1020050127769
申请日：2005-12-22
申请人： 삼성전자주식회사
发明人： 김찬영 , 고승범
IPC分类号： G06F12/00
摘要： A method for ordering and organizing data in a memory device are provided to output data at a high speed by forming data ordering/organization in one control block. A memory cell block arranges a plurality of memory cells. Data line sense amplifiers detect and amplify memory cell data output from the memory cell block. The first control block(320) organizes an output data bit by ordering a sequence of the outputs of the data line sense amplifiers in response to the first ordering/multiplexing signal. The first control block is equipped with a plurality of ordering/multiplexing parts(321-324) receiving a pair of outputs of the data line sense amplifiers and determining whether the output of the received data line sense amplifiers is the first or the fifth output. The second control block(330) organizes the output data bit by ordering the sequence of the outputs of the first control block in the response to the second ordering/multiplexing signal.
摘要翻译：提供了一种用于在存储器件中排序和组织数据的方法，通过在一个控制块中形成数据排序/组织来高速输出数据。存储单元块布置多个存储单元。数据线读出放大器检测并放大从存储单元块输出的存储单元数据。响应于第一排序/复用信号，第一控制块（320）通过排列数据线读出放大器的输出的序列来组织输出数据位。第一控制块配备有接收数据线读出放大器的一对输出的多个排序/复用部分（321-324），并且确定接收的数据线读出放大器的输出是否是第一或第五输出。第二控制块（330）通过在对第二排序/复用信号的响应中排序第一控制块的输出的顺序来组织输出数据位。

8. 发明公开

KR1020150081116A 무선통신 시스템에서 고주파처리 모듈 제어 방법 및 장치 审中-实审
标题翻译：无线通信系统中无线电频率集成电路的控制方法
公开(公告)号：KR1020150081116A
公开(公告)日：2015-07-13
申请号：KR1020140000772
申请日：2014-01-03
申请人： 삼성전자주식회사
发明人： 김찬영
IPC分类号： H04L25/02 , H04L29/10
CPC分类号： H04W48/16
摘要： 본발명은무선통신시스템에서고주파처리모듈제어방법및 장치에관한것으로서, 이동통신단말에서고주파처리모듈을제어하는방법은, 상기고주파처리모듈의신호수신셀을변경하기위한이벤트를감지하는과정과. 타겟셀의정보를기반으로상기타겟셀에대한 SPI(Serial Peripheral Interface) 제어명령이미리저장되어있는지여부를검사하는과정과, 상기타겟셀에대한 SPI 제어명령이미리저장되어있을시, 미리저장된 SPI 제어명령을기반으로상기고주파처리모듈을설정하는과정을포함하여, 동일한 SPI 제어명령을반복적으로생성하는과정을생략함으로써, RFIC 모드전환에소요되는시간을감소시킬수 있다.
摘要翻译：本发明涉及无线通信系统中控制高频处理模块的方法和装置。用于控制无线通信终端中的高频处理模块的方法包括以下步骤：检测事件以改变高频处理模块的信号接收单元; 基于目标小区信息检查是否预先存储针对目标小区的串行外围接口（SPI）控制命令; 并且如果预先存储了目标单元的SPI控制命令，则基于预存的串行外设接口（SPI）控制命令来设置高频处理模块。通过省略重复生成相同SPI控制命令的过程，可以减少切换RFIC模式所需的时间。

9. 发明公开

KR1020080104666A 와이브로 단말기의 로컬 오실레이터 누설 전력을최소화하는 방법 및 장치 无效
标题翻译：用于校准以消除WIBRO终端的本地振荡器漏电功率的方法
公开(公告)号：KR1020080104666A
公开(公告)日：2008-12-03
申请号：KR1020070051739
申请日：2007-05-28
申请人： 삼성전자주식회사
发明人： 조태희 , 김찬영
IPC分类号： H03L1/00 , H03D3/00
CPC分类号： H04B1/0475 , H04B1/30 , H04B17/00
摘要： A method and an apparatus for minimizing local oscillator leakage power of a wibro terminal are provided to minimize LO leakage frequency stably by measuring the power of the LO leakage frequency in an RF output terminal and applying the measured value. A DC voltage value of an I(Inphase) signal and a DC voltage value of a Q(Quadrature) signal in minimizing each DC voltage value are stored when the difference of the DC voltage value between the I signal and Q signal outputted from the RFIC occurs(400). A 2 dimension table using an axis as the I signal and the Q signal based on intermediate values is divided into a quadrant(402). The table is updated by setting a output DC voltage value of the RFIC as the intermediate value of the quadrant, measuring a steady value of the frequency domain spectrum of the I signal and Q signal, and selecting signal values in the quadrant with a small intermediate value among the intermediate values. The division and update process are repeated according the 2 dimension binary search algorithm. The difference between the DC voltage values of I and Q signals about the final stead value and the DC voltage values of the stored I and Q signals(405) according to the result of the repeated process(405).
摘要翻译：提供一种用于最小化振动终端的本地振荡器泄漏功率的方法和装置，用于通过测量RF输出端子中的LO泄漏频率的功率并施加测量值来稳定地最小化LO泄漏频率。当从RFIC输出的I信号和Q信号之间的直流电压值的差异时，存储I（同相）信号的直流电压值和最小化每个直流电压值的Q（正交）信号的直流电压值发生（400）。使用轴作为I信号的二维表和基于中间值的Q信号被划分为象限（402）。通过将RFIC的输出直流电压值设置为象限的中间值来更新表，测量I信号和Q信号的频域频谱的稳定值，并用小中间值选择象限中的信号值中间值之间的值。根据二维二进制搜索算法重新划分和更新过程。根据重复处理（405）的结果，关于最终平稳值的I和Q信号的直流电压值与存储的I和Q信号（405）的DC电压值之间的差异。

10. 发明公开

KR1020070066370A 반도체 메모리 장치의 칼럼선택라인 발생회로 无效
标题翻译：半导体存储器件中的柱塞线控制电路
公开(公告)号：KR1020070066370A
公开(公告)日：2007-06-27
申请号：KR1020050127437
申请日：2005-12-22
申请人： 삼성전자주식회사
发明人： 김찬영 , 고승범
IPC分类号： G11C8/10 , G11C8/12
摘要： A column selection line generation circuit in a semiconductor memory device is provided to improve operation speed of the semiconductor memory device, by advancing enabling time of a column selection line during a normal operation. In a column selection line generation circuit of a semiconductor memory device generating a column selection signal for controlling the electrical connection between a specific bit line and a data input/output line, a decoding part(300) is enabled in response to a column selection line enable signal and generates an output signal responding to a column address specifying the bit line. A driving part(400) is driven to enable the column selection line in response to an output signal of the decoding part, and is disabled in response to the enabling of a repair signal so as to prevent the enabling of the column selection line.
摘要翻译：提供半导体存储器件中的列选择线生成电路，通过在正常操作期间提前列选择线的使能时间来提高半导体存储器件的操作速度。在产生用于控制特定位线和数据输入/输出线之间的电连接的列选择信号的半导体存储器件的列选择线生成电路中，响应于列选择线使能解码部分（300）使能信号并响应指定位线的列地址产生输出信号。驱动部分（400）被驱动以响应于解码部分的输出信号使列选择线响应于修复信号的使能而被禁用，从而阻止列选择线的使能。

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