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1. 发明授权

KR100433437B1 반도체 장치 및 그 제조 방법 및 ＣＭＯＳ 트랜지스터 失效
标题翻译： CMOS图像传感器
公开(公告)号：KR100433437B1
公开(公告)日：2004-05-31
申请号：KR1020010043683
申请日：2001-07-20
申请人： 미쓰비시덴키 가부시키가이샤
发明人： 하야시기요시 , 이노우에야스오
IPC分类号： H01L21/8238
CPC分类号： H01L27/092 , H01L21/28061 , H01L21/823828 , H01L21/823835 , H01L29/4941
摘要： PURPOSE: A semiconductor device having a polymetal gate electrode and a method for manufacturing the same are provided to prevent a formation of a silicide layer at a metal/conductive silicon interface, and to exhibit low-resistance and ohmic characteristics. CONSTITUTION: The polymetal gate electrode is formed on a semiconductor substrate(1), such as a silicon substrate through a gate insulating film(2) such as an oxide film. The polymetal gate electrode has a structure, where a conductive silicon film(3), a silicide film(4), a barrier film(5), and a metal film(6) are laminated sequentially from the semiconductor substrate(1). The conductive silicon film(3) adopts, for example, a poly-Si film, while the silicide film(4) adopts, for example, a WSi film. Also, the barrier film(5) is, for example, a WSiN film and the metal film(6) is, for example, a W film.
摘要翻译：目的：提供具有多金属栅电极的半导体器件及其制造方法，以防止在金属/导电硅界面处形成硅化物层，并呈现低电阻和欧姆特性。构成：通过氧化膜等的栅极绝缘膜（2），在硅基板等半导体基板（1）上形成多金属栅电极。多晶硅栅电极具有从半导体衬底（1）依次层叠导电性硅膜（3），硅化物膜（4），阻挡膜（5）和金属膜（6）的结构。导电硅膜（3）例如采用多晶硅膜，而硅化物膜（4）采用例如WSi膜。另外，阻挡膜（5）例如是WSiN膜，金属膜（6）例如是W膜。

2. 发明公开

KR1019980024028A 불휘발성 반도체 기억 장치 失效
公开(公告)号：KR1019980024028A
公开(公告)日：1998-07-06
申请号：KR1019970019740
申请日：1997-05-21
申请人： 미쓰비시덴키 가부시키가이샤
发明人： 오나카도다카히로 , 다카다히로시 , 하야시기요시
IPC分类号： H01L27/115
摘要： 기입작동후의 한계치 전압의 분포폭을 좁게 한다.
선택 메모리셀이 연결되어 있는 열선(SBN)(column line)에 메모리셀 트랜지스터와 채널전도형이 다른 선택게이트 트랜지스터(selector gate transistor)(NSG)를 통해 기입 바이어스전압(write bias voltag)(VSBL)을 공급한다. 상기 선택게이트 트랜지스터( NSG)의 전류구동력(current drivability)은, 메모리셀의 리크전류(leak current) 보다도 크고, 또한 채널형성시의 채널전류 보다도 작은 전류를 공급하도록 된다. 선택워드선에, 패리티전압(parity voltage)을 인가하면 채널형성시 큰 채널전류가 흘러 부비트선(subbit line) 전위가 변화하여 기입이 억제된다.
이것에 의해, 기입후 한계치 전압분포폭을 좁게 한다.

3. 发明授权

KR100248689B1 불휘발성 반도체 기억 장치 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：KR100248689B1
公开(公告)日：2000-03-15
申请号：KR1019970019740
申请日：1997-05-21
申请人： 미쓰비시덴키 가부시키가이샤
发明人： 오나카도다카히로 , 다카다히로시 , 하야시기요시
IPC分类号： H01L27/115
CPC分类号： G11C16/3486 , G11C16/0416 , G11C16/3468
摘要： To a column line to which a selected memory cell is connected, a write bias voltage is supplied through a selection gate transistor having different channel conductivity type than the memory cell transistor. Current drivability of the selection gate transistor is adapted to be larger than a leak current of the memory cell and to supply a current smaller than the channel current when a channel is formed in one aspect. When a verifying voltage is applied to the selected word line, a large channel current flows when a channel is formed, potential of a subbit line is changed accordingly, and programming is suppressed. In another aspect, the selection gate transistor serves as a constant current source to make the programming speed of the memory cells constant. Thus distribution of threshold values after programming can be made narrow.

4. 发明公开

KR1020020008771A 반도체 장치 및 그 제조 방법 및 ＣＭＯＳ 트랜지스터 失效
标题翻译：半导体器件及其制造方法和CMOS晶体管
公开(公告)号：KR1020020008771A
公开(公告)日：2002-01-31
申请号：KR1020010043683
申请日：2001-07-20
申请人： 미쓰비시덴키 가부시키가이샤
发明人： 하야시기요시 , 이노우에야스오
IPC分类号： H01L21/8238
CPC分类号： H01L27/092 , H01L21/28061 , H01L21/823828 , H01L21/823835 , H01L29/4941
摘要： PURPOSE: A semiconductor device having a polymetal gate electrode and a method for manufacturing the same are provided to prevent a formation of a silicide layer at a metal/conductive silicon interface, and to exhibit low-resistance and ohmic characteristics. CONSTITUTION: The polymetal gate electrode is formed on a semiconductor substrate(1), such as a silicon substrate through a gate insulating film(2) such as an oxide film. The polymetal gate electrode has a structure, where a conductive silicon film(3), a silicide film(4), a barrier film(5), and a metal film(6) are laminated sequentially from the semiconductor substrate(1). The conductive silicon film(3) adopts, for example, a poly-Si film, while the silicide film(4) adopts, for example, a WSi film. Also, the barrier film(5) is, for example, a WSiN film and the metal film(6) is, for example, a W film.
摘要翻译：目的：提供一种具有多金属栅电极的半导体器件及其制造方法，以防止在金属/导电硅界面处形成硅化物层，并且具有低电阻和欧姆特性。构成：多金属栅电极通过栅极绝缘膜（2）如氧化膜形成在诸如硅衬底的半导体衬底（1）上。多金属栅电极具有从半导体衬底（1）依次层叠导体硅膜（3），硅化物膜（4），阻挡膜（5）和金属膜（6）的结构。导电性硅膜（3）例如采用多晶硅膜，而硅化物膜（4）采用例如WSi膜。此外，阻挡膜（5）例如是WSiN膜，金属膜（例如）为例如W膜。

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