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61. 发明公开

KR1020000027512A 반도체 소자의 제조방법 无效
标题翻译：制造半导体器件的方法
公开(公告)号：KR1020000027512A
公开(公告)日：2000-05-15
申请号：KR1019980045457
申请日：1998-10-28
申请人： 에스케이하이닉스 주식회사
发明人： 김형균 , 김우진 , 기영종 , 공영택
IPC分类号： H01L21/336
摘要： PURPOSE: A method of manufacturing a semiconductor device is provided to prevent fluorine ions from penetrating a gate insulating layer in a thermal process for manufacturing a gate electrode and a leakage current. CONSTITUTION: A method of manufacturing a semiconductor device comprises the steps of: forming a gate insulating layer(12) on a semiconductor substrate(11); forming a silicon layer(13) doped with impurities on the gate insulating layer; forming a tungsten silicide layer(14) on the doped polysilicon layer; performing a thermal process of the resulting semiconductor substrate for a predetermined time; and forming a gate electrode by patterning the tungsten silicide layer and the polysilicon layer doped impurities. The thermal process is carried out for 5 to 60 minutes after the temperature of the chamber in which the tungsten silicide layer is formed is elevated in the speed of 50 to 200°C/min until 1000 to 1200°C.
摘要翻译：目的：提供一种制造半导体器件的方法，以防止在用于制造栅电极的热处理中的氟离子渗透栅极绝缘层和漏电流。构成：制造半导体器件的方法包括以下步骤：在半导体衬底（11）上形成栅极绝缘层（12）; 在所述栅极绝缘层上形成掺杂有杂质的硅层（13）; 在所述掺杂多晶硅层上形成硅化钨层（14）; 对所得到的半导体衬底进行预定时间的热处理; 以及通过图案化硅化钨层和掺杂多晶硅层的杂质形成栅电极。在其中形成硅化钨层的室的温度以50至200℃/ min的速度升高至1000至1200℃之后，进行热处理5至60分钟。

62. 发明公开

KR1020000024908A 반도체 장치의 게이트 전극 형성 방법 无效
标题翻译：形成半导体器件栅极电极的方法
公开(公告)号：KR1020000024908A
公开(公告)日：2000-05-06
申请号：KR1019980041711
申请日：1998-10-02
申请人： 에스케이하이닉스 주식회사
发明人： 김형균 , 기영종 , 김우진 , 김동준
IPC分类号： H01L21/336
摘要： PURPOSE: A method for forming gate electrode of semiconductor device is provided to prevent a quality decrease and a fault of a gate oxidation film by performing an annealing process over 5 minutes in a low atmosphere pressure and high temperature vacuum condition before the performance of a spacer process. CONSTITUTION: A gate insulating film(14') is etched for performing a self-align to a gate electrode (20') and a reside of a substrate surface is removed using a wet cleaning process. An annealing process is performed over 5 minutes in a low atmosphere pressure and high temperature vacuum condition before the performance of a spacer process, and then a fluorine is removed from a surface of a tungsten silicide film. A silicon nitration film(22') is deposited at 500 to 2000 angstrom thickness using a low pressure chemical vapor deposition. The silicon nitration film(22') is etched using a dry etching process and then a spacer is formed to a side wall portion of the gate electrode(20').
摘要翻译：目的：提供一种形成半导体器件的栅电极的方法，用于在执行间隔件之前，在低气压和高温真空条件下，在5分钟内进行退火处理，防止栅极氧化膜的质量下降和故障处理。构成：蚀刻栅极绝缘膜（14'）以对栅电极（20'）进行自对准，并且使用湿式清洗工艺去除衬底表面的驻留。在执行间隔物工艺之前，在低气压和高温真空条件下进行5分钟的退火处理，然后从硅化钨膜的表面除去氟。使用低压化学气相沉积以500至2000埃的厚度沉积硅化硝化膜（22'）。使用干蚀刻工艺蚀刻硅化硝化膜（22'），然后在栅电极（20'）的侧壁部分形成间隔物。

63. 发明授权

KR102001597B1 반도체 장치 및 그 제조 방법 有权
公开(公告)号：KR102001597B1
公开(公告)日：2019-07-19
申请号：KR1020120143247
申请日：2012-12-11
申请人： 에스케이하이닉스 주식회사
发明人： 김재수 , 김형균
IPC分类号： H01L21/762

64. 发明授权

KR101907070B1 반도체 장치 및 그 제조방법 有权
公开(公告)号：KR101907070B1
公开(公告)日：2018-10-11
申请号：KR1020120057433
申请日：2012-05-30
申请人： 에스케이하이닉스 주식회사
发明人： 김형균
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L29/4236 , H01L21/76232 , H01L27/10876 , H01L29/665 , H01L29/6656 , H01L29/78
摘要： 본기술은반도체장치의집적도가증가하더라도실리사이드막에의한콘택저항감소가용이한반도체장치및 그제조방법을제공하기위한것으로, 활성영역을갖는기판; 상기활성영역의표면에형성된실리사이드막; 상기실리사이드막과상기기판이식각되어형성된트렌치; 상기트렌치내부에형성된매립게이트; 상기기판전면에형성된층간절연막; 및상기층간절연막에형성되어상기실리사이드막을노출시키는오픈영역을포함하는반도체장치를제공한다.

65. 发明公开

KR1020140083746A 보이드 프리 폴리실리콘 갭필 방법 및 그를 이용한 반도체장치 제조 방법 审中-实审
标题翻译：使用无机多晶硅和MEHTO制造半导体器件的方法
公开(公告)号：KR1020140083746A
公开(公告)日：2014-07-04
申请号：KR1020120153822
申请日：2012-12-26
申请人： 에스케이하이닉스 주식회사
发明人： 김형균
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L21/76897 , H01L21/28079 , H01L21/28088 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/324 , H01L21/76802 , H01L21/7682 , H01L21/76831 , H01L21/76847 , H01L21/76883 , H01L27/1085 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/228 , H01L27/2436
摘要： The present technique provides a method of forming a polysilicon layer which prevents the void of polysilicon and a method of fabricating a semiconductor device using the same. A method of fabricating a semiconductor device according to the present technique includes a step of forming a filing gate electrode in a semiconductor substrate, a step of forming an insulating layer in the upper part of the filling gate electrode, a step of forming a contact hole which exposes the semiconductor substrate by etching the insulating layer, a step of forming a sacrifice spacer in the sidewall of the contact hole, a step of forming a recessed polysilicon layer pattern in the contact hole, a step of forming an air gap by removing the sacrifice spacer, and a step of removing a seam existing in the polysilicon layer pattern by performing a thermal process.
摘要翻译：本技术提供了形成防止多晶硅空隙的多晶硅层的方法以及使用其制造半导体器件的方法。根据本技术的制造半导体器件的方法包括在半导体衬底中形成栅极电极的步骤，在填充栅电极的上部形成绝缘层的步骤，形成接触孔的步骤其通过蚀刻绝缘层而暴露半导体衬底，在接触孔的侧壁中形成牺牲间隔物的步骤，在接触孔中形成凹陷多晶硅层图案的步骤，通过去除形成空隙的步骤牺牲间隔物，以及通过进行热处理去除多晶硅层图案中存在的接缝的步骤。

66. 发明公开

KR1020130134140A 반도체 장치 및 그 제조방법 审中-实审
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020130134140A
公开(公告)日：2013-12-10
申请号：KR1020120057433
申请日：2012-05-30
申请人： 에스케이하이닉스 주식회사
发明人： 김형균
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L29/4236 , H01L21/76232 , H01L27/10876 , H01L29/665 , H01L29/6656 , H01L29/78
摘要： Provided are a semiconductor and a manufacturing method capable of easily decreasing contact resistance caused by a silicide film when the integration of the semiconductor is increased. The semiconductor comprises a substrate, the silicide film, a trench, a buried gate, an interlayer insulating film, and an open area. The substrate has an active area. The silicide film is formed on the surface of the active area. The trench is formed by etching the silicide film and the substrate. The buried gate is formed inside the trench. The interlayer insulating film is formed on the front of the substrate. The open area is formed on the interlayer insulating film and exposes the silicide film.
摘要翻译：提供了当半导体的集成增加时能够容易地降低由硅化物膜引起的接触电阻的半导体和制造方法。半导体包括衬底，硅化物膜，沟槽，掩埋栅极，层间绝缘膜和开放区域。基板具有有效面积。硅化物膜形成在有源区的表面上。通过蚀刻硅化物膜和衬底形成沟槽。埋入栅极形成在沟槽内。层间绝缘膜形成在基板的前面。在层间绝缘膜上形成开放区域，使硅化物膜露出。

67. 发明公开

KR1020110102727A 매립 게이트형 반도체 소자의 제조방법 无效
标题翻译：制造BIGIED GATE半导体器件的方法
公开(公告)号：KR1020110102727A
公开(公告)日：2011-09-19
申请号：KR1020100021889
申请日：2010-03-11
申请人： 에스케이하이닉스 주식회사
发明人： 김형균 , 조호진
IPC分类号： H01L21/336
CPC分类号： H01L21/28238 , H01L21/28247 , H01L29/4236
摘要： 본 발명은 게이트 전극물질의 보이드를 방지할 수 있는 매립 게이트형 반도체 소자의 제조방법을 개시한다. 매립 게이트형 반도체 소자의 제조방법은 반도체 기판을 일정 깊이로 식각하여 트렌치를 형성하는 단계, 상기 트렌치의 저부에 배리어막을 형성하는 단계, 상기 배리어막이 형성된 트렌치가 매립되도록 게이트 전극물질을 형성하는 단계 및 상기 게이트 전극물질을 식각하여 상기 배리어막상에 게이트 전극을 형성하는 단계를 포함한다.

68. 发明公开

KR1020110000146A 반도체 소자의 제조방법 失效
标题翻译：制造半导体器件的方法
公开(公告)号：KR1020110000146A
公开(公告)日：2011-01-03
申请号：KR1020090057524
申请日：2009-06-26
申请人： 에스케이하이닉스 주식회사
发明人： 김형균 , 정용수
IPC分类号： H01L21/336 , H01L21/8242
CPC分类号： H01L27/10894 , H01L27/10888
摘要： PURPOSE: A method for manufacturing a semiconductor device is provided to prevent the generation of over-etching related defects by reducing the thickness of an oxide film grown on a poly-silicon film for bit-line contact. CONSTITUTION: An interlayer insulating film(25) is formed on the cell region and the peripheral region of a substrate(20). A bit-line contact hole(26) exposing a part of the substrate in the cell region is formed in the interlayer insulating film. A first poly-silicon film(27A) is formed on the cell region and the peripheral region. A second poly-silicon film is formed on the cell region and the peripheral region. The second poly-silicon film, the first poly-silicon film, and the interlayer insulating film are eliminated. A gate oxide film(28A) is formed in the peripheral region.
摘要翻译：目的：提供一种用于制造半导体器件的方法，以通过减少在用于位线接触的多晶硅膜上生长的氧化膜的厚度来防止产生过蚀刻相关缺陷。构成：在基板（20）的单元区域和周边区域上形成层间绝缘膜（25）。在层间绝缘膜中形成露出单元区域中的一部分基板的位线接触孔（26）。在单元区域和周边区域上形成第一多晶硅膜（27A）。在单元区域和周边区域上形成第二多晶硅膜。消除第二多晶硅膜，第一多晶硅膜和层间绝缘膜。在周边区域形成栅极氧化膜（28A）。

69. 发明授权

KR100977633B1 반도체 소자의 제조방법 失效
标题翻译：制造半导体器件的方法
公开(公告)号：KR100977633B1
公开(公告)日：2010-08-24
申请号：KR1020080021595
申请日：2008-03-07
申请人： 에스케이하이닉스 주식회사
发明人： 김형균 , 조규동
IPC分类号： H01L21/76
摘要： 본 발명은 반도체 소자의 제조방법을 개시한다. 개시된 본 발명의 방법은, 식각 대상층을 식각하여 홀을 형성하는 단계와, 상기 홀의 표면을 따라 질화막을 형성하는 단계와, 상기 질화막이 형성된 홀 내에 HDP 절연막을 매립하는 단계와, 상기 HDP 절연막이 형성된 식각 대상층에 산화 공정을 수행하여 상기 HDP 절연막의 매립시 식각 대상층의 표면 상에 조각 형태로 잔류된 질화막 부분을 산화시킴과 아울러 상기 식각 대상층 상부에 희생 산화막을 형성하는 단계 및 상기 산화된 질화막을 포함하여 희생 산화막을 제거하는 단계를 포함한다.
摘要翻译：本发明公开了一种制造半导体器件的方法。本发明的方法中所公开的，该方法包括蚀刻所述蚀刻目标层，以形成一个孔，并形成根据孔表面上的氮化物膜的步骤，该方法包括在该氮化物膜形成的孔中填充的HDP绝缘膜，形成在HDP电介质膜，通过HDP包括步骤期间嵌入，并且用于氧化残留在片形式的绝缘膜的蚀刻对象层的表面上的氮化物层部分被蚀刻层上上形成以及牺牲氧化膜的氧化氮化硅膜的蚀刻目标层上执行氧化过程并去除牺牲氧化膜。

70. 发明公开

KR1020090017917A 반도체 소자의 소자분리막 형성방법 无效
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：KR1020090017917A
公开(公告)日：2009-02-19
申请号：KR1020070082441
申请日：2007-08-16
申请人： 에스케이하이닉스 주식회사
发明人： 조규동 , 김형균 , 조호진 , 김현정
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L21/02282 , H01L21/0234
摘要： A method of forming the device isolation film in the semiconductor device is provided to physically reinforce the linear nitride film by processes the linear nitride film by plasma nitridation. The trench is formed in the semiconductor substrate(100). The side wall oxide(130) is formed in the trench surface. The linear nitride film(140) is formed on the side wall oxide. The fluid insulating layer is formed on the linear nitride film to fill the trench. The fluid dielectric is etched and then the linear nitride film is exposed. The plasma nitridation is preformed on the exposed linear nitride film. The densified insulating layer is formed on the nitrified linear nitride film and fluid dielectric to fill the trench.
摘要翻译：提供了在半导体器件中形成器件隔离膜的方法，通过等离子体氮化处理线性氮化物膜来物理地加强线状氮化物膜。沟槽形成在半导体衬底（100）中。侧壁氧化物（130）形成在沟槽表面中。线状氮化物膜（140）形成在侧壁氧化物上。流体绝缘层形成在线状氮化物膜上以填充沟槽。蚀刻流体电介质，然后暴露线性氮化物膜。在暴露的线性氮化物膜上进行等离子体氮化。在氮化的线性氮化物膜和流体电介质上形成致密的绝缘层以填充沟槽。

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