专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

KR101403314B1 메모리 장치 및 데이터 비트 저장 방법 有权
标题翻译：存储器件和存储数据位的方法
公开(公告)号：KR101403314B1
公开(公告)日：2014-06-05
申请号：KR1020080048267
申请日：2008-05-23
申请人： 삼성전자주식회사
发明人： 설광수 , 박성일 , 조경래 , 조인성
IPC分类号： G11C16/04 , G11C16/08 , G11C29/42
CPC分类号： H03M13/611 , G06F11/1072 , G11C7/1006 , G11C11/5642 , G11C16/26 , G11C29/00 , H03M13/13 , H03M13/15 , H03M13/27 , H03M13/2732 , H03M13/2906 , H03M13/3707 , H03M13/3715 , H03M13/47
摘要： 메모리 장치 및 메모리 데이터 비트 저장 방법이 제공된다. 본 발명의 메모리 장치는 복수의 멀티 레벨 셀들을 포함하는 멀티 레벨 셀 어레이, 상기 멀티 레벨 셀에 기록하기 위한 데이터를 인코딩하여 코드 워드(code word)로 변환하는 에러 정정부, 상기 코드 워드에 포함된 에러 패턴에 대응하는 제1 데이터 패턴을 분석하는 에러 패턴 분석부, 및 상기 분석된 제1 데이터 패턴을 제2 데이터 패턴으로 변환하는 데이터 변환부를 포함하며, 이를 통해 데이터의 장기간 유지 시 발생할 수 있는 데이터 에러를 효율적으로 줄일 수 있어 메모리 장치의 신뢰성을 향상시킬 수 있다.
멀티 레벨 셀, 멀티 레벨 셀, 신뢰성, 에러 패턴, 전하 트랩형 플래시

92. 发明公开

KR1020130042272A 3차원 반도체 메모리 장치 审中-实审
标题翻译：三维半导体存储器件
公开(公告)号：KR1020130042272A
公开(公告)日：2013-04-26
申请号：KR1020110106460
申请日：2011-10-18
申请人： 삼성전자주식회사
发明人： 심선일 , 윤장근 , 최정혁 , 최정달 , 장재훈 , 설광수
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： G11C16/0466 , G11C16/0483 , H01L23/535 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L2924/0002 , H01L21/823487 , H01L2924/00
摘要： PURPOSE: A three dimensional semiconductor memory device is provided to improve the integration degree by using a cell strings for sharing a bit ine and a string selection line. CONSTITUTION: An electrode structure is vertically laminated on a substrate. First and second semiconductor pillars(STR1,STR2) penetrate the electrode structure. A data storing layer is formed between the first and second semiconductor pillars. A bit line(BL0,BL1) is commonly connected to the first and second semiconductor pillars. First and second string selection transistors(SST0,SST1) are serially connected.
摘要翻译：目的：提供三维半导体存储器件，以通过使用用于共享位元和串选择线的单元串来提高积分度。构成：将电极结构垂直层压在基板上。第一和第二半导体柱（STR1，STR2）穿透电极结构。在第一和第二半导体柱之间形成数据存储层。位线（BL0，BL1）通常连接到第一和第二半导体柱。第一和第二串选择晶体管（SST0，SST1）串联。

93. 发明公开

KR1020090122063A 메모리 장치 및 데이터 비트 저장 방법 有权
标题翻译：存储器件和存储数据位的方法
公开(公告)号：KR1020090122063A
公开(公告)日：2009-11-26
申请号：KR1020080048267
申请日：2008-05-23
申请人： 삼성전자주식회사
发明人： 설광수 , 박성일 , 조경래 , 조인성
IPC分类号： G11C16/04 , G11C16/08 , G11C29/42
CPC分类号： H03M13/611 , G06F11/1072 , G11C7/1006 , G11C11/5642 , G11C16/26 , G11C29/00 , H03M13/13 , H03M13/15 , H03M13/27 , H03M13/2732 , H03M13/2906 , H03M13/3707 , H03M13/3715 , H03M13/47
摘要： PURPOSE: A memory device and a method of storing data bit are provided to efficiently decrease data errors that may happen while maintaining data for a long time so that the reliability of a memory device may be increased. CONSTITUTION: A memory device(100) includes a multi-level cell array(110), an error correction unit(120), an error pattern analysis unit(130) and a data converter(140). The multi-level cell array includes plural multi-level cells, and the error collection unit encodes the data for the recording on a multi-level cell to convert a code word. The error pattern analysis unit analyzes the first data pattern corresponding to an error pattern included in the cord word. The data converter converts the first data pattern into the second data pattern.
摘要翻译：目的：提供存储器件和存储数据位的方法，以有效地降低在长时间保持数据时可能发生的数据错误，从而可以增加存储器件的可靠性。构成：存储装置（100）包括多级单元阵列（110），纠错单元（120），误差模式分析单元（130）和数据转换器（140）。多级单元阵列包括多个多电平单元，并且错误收集单元对用于在多电平单元上进行记录的数据进行编码以转换代码字。误差模式分析单元分析与包含在帘线字中的错误模式对应的第一数据模式。数据转换器将第一数据模式转换成第二数据模式。

94. 发明公开

KR1020090122060A 오류 정정 장치, 그 방법 및 상기 장치를 포함하는 메모리장치 有权
标题翻译：错误校正装置，包含装置的方法和存储装置
公开(公告)号：KR1020090122060A
公开(公告)日：2009-11-26
申请号：KR1020080048264
申请日：2008-05-23
申请人： 삼성전자주식회사
发明人： 설광수 , 박성일 , 조경래
IPC分类号： G11C29/42 , G11C16/04
CPC分类号： G11C16/26 , G06F11/1072 , G11C11/5642 , G11C29/00 , G11C2211/5634
摘要： PURPOSE: An error correction apparatus, a method thereof and a memory device comprising the apparatus are provided to select a cord word corresponding to a reading word based on a selected reading error pattern when a reading error read from a multi-level cell does not exist in an error correction capability range. CONSTITUTION: An error correction device(120) includes a judgment unit(121), a reading voltage control unit(122) and a cord word determining unit(123). The judgment unit judges whether or not read words from a multi-level cell exists in an error correction capability range. The reading voltage control unit increases or decreases the reading voltage applied to a multi-level cell in case that the reading word does not exist in the error correction capability range. The cord word determining unit analyzes a bit error depending on the increase or decrease of the reading voltage, and selects the cord words based on the selected reading error pattern by corresponding to the analyzed bit error.
摘要翻译：目的：提供一种纠错装置，其方法和包括该装置的存储装置，用于当不存在从多级单元读取的读取错误时，基于所选择的读取错误模式来选择与读取字对应的绳索字在纠错能力范围内。构成：纠错装置（120）包括判断单元（121），读取电压控制单元（122）和电话词确定单元（123）。判断单元判断来自多级单元的读取字是否存在于纠错能力范围内。读取电压控制单元增加或减少在纠错能力范围内不存在读取字的情况下施加到多电平单元的读取电压。绳字确定单元根据读取电压的增加或减少来分析位错误，并且通过对应于分析的位错误，基于所选择的读取错误模式来选择线字。

95. 发明公开

KR1020090102262A 전하의 측면 이동을 줄일 수 있는 메모리 장치의 작동 방법 有权
标题翻译：存储器件的操作方法减少了电荷的横向运动
公开(公告)号：KR1020090102262A
公开(公告)日：2009-09-30
申请号：KR1020080027592
申请日：2008-03-25
申请人： 삼성전자주식회사
发明人： 설광수 , 진영구 , 박윤동
IPC分类号： G11C16/34 , G11C16/10 , G11C16/12
CPC分类号： G11C16/10 , G11C16/3409 , G11C16/344 , G11C16/3454
摘要： PURPOSE: A method for operating a memory device is provided to implement a negative valid effect test voltage below 0 V while applying the voltage of 0V or more to a control gate of the memory cell. CONSTITUTION: A pre-program voltage is applied to a memory cell of an erase state(S110). The memory cell is pre-programmed to have a smaller threshold voltage distribution in comparison with the erase state. Whether the memory cell is pre-programmed is verified using the negative valid verification voltage(S130).
摘要翻译：目的：提供一种用于操作存储器件的方法，以在0V以上的电压施加到存储器单元的控制栅极的情况下实现低于0V的负有效效应测试电压。构成：将预编程电压施加到擦除状态的存储单元（S110）。与擦除状态相比，存储器单元被预编程为具有较小的阈值电压分布。使用负有效验证电压验证存储器单元是否被预编程（S130）。

96. 发明公开

KR1020090027140A 비휘발성 메모리 소자의 프로그램 방법 有权
标题翻译：非易失性存储器件的编程方法
公开(公告)号：KR1020090027140A
公开(公告)日：2009-03-16
申请号：KR1020080071896
申请日：2008-07-23
申请人： 삼성전자주식회사
发明人： 설광수 , 박상진 , 최기환 , 성정헌 , 최상무
IPC分类号： G11C16/34 , G11C16/12 , G11C16/10
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/0483 , G11C16/12
摘要： A programming method of a non volatile memory device is provided to prevent an over program by saturating a threshold voltage within a fast time. A programming method of a non volatile memory device comprises the following steps: a step for supplying a program voltage to a memory cell(S10); a step for supplying a supplement pulse in order to stabilize a charge after supplying the program voltage(S30); a step for supplying a recovery voltage to the memory cell after supplying the supplement pulse(S40); and a step for supplying a verification voltage after supplying the recovery voltage(S50).
摘要翻译：提供了非易失性存储器件的编程方法，以通过在快速时间内饱和阈值电压来防止过度程序。非易失性存储器件的编程方法包括以下步骤：向存储器单元提供编程电压的步骤（S10）; 提供辅助脉冲以便在提供编程电压之后稳定电荷的步骤（S30）; 在提供补充脉冲之后，向存储单元提供恢复电压的步骤（S40）; 以及在提供恢复电压之后提供验证电压的步骤（S50）。

97. 发明公开

KR1020090022191A 비휘발성 메모리 소자의 프로그램 방법 有权
标题翻译：非易失性存储器件的编程方法
公开(公告)号：KR1020090022191A
公开(公告)日：2009-03-04
申请号：KR1020070087312
申请日：2007-08-29
申请人： 삼성전자주식회사
发明人： 박상진 , 설광수 , 성정헌
IPC分类号： G11C16/34 , G11C16/10 , G11C16/12
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3454
摘要： A programming method of a non volatile memory device is provided to saturate a threshold voltage within a fast time and to hasten stabilization of a charge by adding a perturbation pulse. In a first programming step(S100), a program voltage is supplied to a memory cell, and is verified by a first verification voltage. A perturbation pulse for hastening stabilization of a charge is supplied to the memory cell passing verification using the first verification voltage(S200). After the perturbation pulse is supplied, the program voltage is verified by a second verification voltage larger than the first verification voltage(S300). When the program voltage does not pass the verification using the second verification voltage, a program voltage is supplied to the memory cell, receives a perturbation pulse, and is verified by the second verification voltage again(S500).
摘要翻译：提供了一种非易失性存储器件的编程方法，以在快速时间内使阈值电压饱和，并通过加入扰动脉冲来加速电荷的稳定。在第一编程步骤（S100）中，将编程电压提供给存储单元，并通过第一验证电压进行验证。用于加速电荷稳定的扰动脉冲被提供给使用第一验证电压的存储器单元通过验证（S200）。在提供扰动脉冲之后，通过大于第一验证电压的第二验证电压验证编程电压（S300）。当编程电压不通过使用第二验证电压的验证时，将编程电压提供给存储单元，接收扰动脉冲，并再次通过第二验证电压进行验证（S500）。

98. 发明公开

KR1020090022170A 알루미늄 산화물층 형성방법 및 이를 이용한 전하 트랩형메모리 소자의 제조 방법 有权
标题翻译：形成氧化铝层的方法和使用它的制造电荷捕获存储器件
公开(公告)号：KR1020090022170A
公开(公告)日：2009-03-04
申请号：KR1020070087290
申请日：2007-08-29
申请人： 삼성전자주식회사
发明人： 최상무 , 설광수 , 신웅철 , 박상진 , 이은하 , 성정헌
IPC分类号： H01L21/316 , H01L21/8247 , H01L27/115 , B82Y40/00
CPC分类号： H01L21/28282 , H01L21/02178 , H01L21/02263 , H01L21/02356 , H01L21/02362 , H01L21/31604 , H01L21/3162 , H01L21/28141
摘要： A method for forming aluminum oxide layer and a method for manufacturing a charge trap memory device using the same are provided to prevent a defect like the warpage of the substrate by reducing a temperature for forming the aluminum oxide layer by using an auxiliary layer. An amorphous aluminum oxide layer(12a) is formed in a lower layer(10). A crystalline sacrificial layer is formed on the amorphous aluminum oxide layer. The amorphous aluminum oxide layer is crystallized. The lower layer is made of the charge storage material. The amorphous chromium oxide layer forms a chromium oxide layer(14) having an alpha crystal structure by the first thermal processing. The charge storage material is the silicon nitride. The amorphous auxiliary layer is formed on the amorphous aluminum oxide layer. The densification process for the amorphous aluminum oxide layer is performed before the crystalline auxiliary layer is formed.
摘要翻译：提供一种形成氧化铝层的方法以及使用该氧化铝层的电荷阱存储装置的制造方法，通过使用辅助层降低形成氧化铝层的温度来防止像基板的翘曲那样的缺陷。在下层（10）中形成无定形氧化铝层（12a）。在非晶态氧化铝层上形成晶体牺牲层。无定形氧化铝层结晶。下层由电荷存储材料制成。无定形氧化铬层通过第一次热处理形成具有α晶体结构的氧化铬层（14）。电荷存储材料是氮化硅。无定形辅助层形成在无定形氧化铝层上。无定形氧化铝层的致密化处理在形成结晶性辅助层之前进行。

99. 发明公开

KR1020090021067A 결정질 알루미늄 산화물층의 에너지 밴드 갭을 높이는 방법및 에너지 밴드 갭이 높은 결정질 알루미늄 산화물층을포함하는 전하 트랩 메모리 소자의 제조 방법 有权
标题翻译：增加晶体氧化铝层的能量带隙的方法和包含具有高能带隙的结晶氧化铝层的充电陷阱存储器件的方法
公开(公告)号：KR1020090021067A
公开(公告)日：2009-02-27
申请号：KR1020080039458
申请日：2008-04-28
申请人： 삼성전자주식회사
发明人： 최상무 , 설광수 , 신웅철 , 박상진 , 성정헌
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L21/28282 , H01L21/0223 , H01L21/0226 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： A method of increasing energy band gap of a crystalline aluminum oxide layer and a method of manufacturing a charge trap memory device comprising a crystalline aluminum oxide layer having high energy band gap are provided to increase an energy band gap of a crystalline aluminum oxide layer by forming a crystalline aluminum oxide layer with a wet oxidation process and a thermal process. An amorphous aluminum oxide layer(20b) is formed on an underlayer(18) in order to enhance energy band gap of an aluminum oxide layer. Hydrogen(H) or hydroxyl radical(OH) is introduced within the amorphous aluminum oxide layer. The amorphous aluminum oxide layer is crystallized. The hydrogen or the hydroxyl radical is injected with one method among wet-oxidization, ion implantation and plasma doping. The aluminum oxide layer is heat-treated in 800~1300°C.
摘要翻译：提供一种提高结晶性氧化铝层的能带隙的方法以及制造包含具有高能带隙的结晶氧化铝层的电荷陷阱存储器件的方法，以通过形成结晶氧化铝层来增加结晶氧化铝层的能带隙具有湿氧化工艺和热处理的结晶氧化铝层。在底层（18）上形成无定形氧化铝层（20b），以增强氧化铝层的能带隙。在无定形氧化铝层内引入氢（H）或羟基（OH）。无定形氧化铝层结晶。在湿氧化，离子注入和等离子体掺杂中，用一种方法注入氢或羟基。氧化铝层在800〜1300℃下进行热处理。

100. 发明公开

KR1020090020129A 전하 트랩층을 가지는 비휘발성 메모리 소자 및 그 제조방법 无效
标题翻译：具有电荷捕获层的非易失性存储器件及其制造方法
公开(公告)号：KR1020090020129A
公开(公告)日：2009-02-26
申请号：KR1020070084600
申请日：2007-08-22
申请人： 삼성전자주식회사
发明人： 최상무 , 설광수 , 박상진 , 성정헌
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L21/28282 , H01L29/792 , H01L29/4234 , H01L29/66833
摘要： A non-volatile memory device and a manufacturing method thereof are provided to prevent the leakage of electric charge and the delay of operating speed by trapping the electric charge to the deformity level of the specific energy level. A gate structure(20) comprises a charge trapping layer(23) including a crystalline substance. The charge trapping layer comprises the crystalline substance formed on a tunneling insulating layer(21). A blocking insulation layer(25) is formed on the charge trapping layer. A gate electrode(27) is formed on the blocking insulation layer. The first and second impurity regions(13,15) are formed in a substrate(11) in order to contact the tunneling insulating layer. The gate electrode comprises the TaN metal layer. The charge trapping layer comprises the crystalline silicon nitride.
摘要翻译：提供一种非易失性存储器件及其制造方法，以通过将电荷俘获到特定能级的畸形水平来防止电荷的泄漏和操作速度的延迟。栅极结构（20）包括包含结晶物质的电荷捕获层（23）。电荷捕获层包括在隧道绝缘层（21）上形成的结晶物质。在电荷俘获层上形成阻挡绝缘层（25）。栅极电极（27）形成在阻挡绝缘层上。第一和第二杂质区（13,15）形成在衬底（11）中，以便与隧道绝缘层接触。栅电极包括TaN金属层。电荷捕获层包括晶体氮化硅。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式