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1. 发明公开

KR1020010076221A 반도체 장치 및 그 제조 방법 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020010076221A
公开(公告)日：2001-08-11
申请号：KR1020000062580
申请日：2000-10-24
申请人： 미쓰비시덴키 가부시키가이샤
发明人： 구로이다까시 , 호리따가쯔유끼 , 우에노슈이찌 , 시오자와가쯔오미
IPC分类号： H01L29/78
摘要： PURPOSE: To realize a MOSFET, which can increase its on-current and can reduce its off-current, by a method, where the threshold voltage of the ends of a channel region is made low in comparison with the threshold voltage of the center of the channel region. CONSTITUTION: In a MOSFET 201, the value of a unit capacitor, which is formed by a gate electrode 13 and the surface of a semiconductor substrate 1 via a second gate insulating film 10, can be made higher than that value of a unit capacitor, which is formed by the gate electrode 13 and the surface of the substrate 1 via first gate insulating films 7. As the dielectric contact of a silicon nitride film, which is used for films 7, is higher than the dielectric constant of a silicon oxide film, which is used for the film 10, it is easy to obtain this relation between the sized of the above two-unit capacitors.
摘要翻译：目的：通过一种方法实现一种可以增加其导通电流并可以减少其截止电流的MOSFET，其中通道区域的端部的阈值电压与中心点的阈值电压相比较低通道区域。构成：在MOSFET201中，能够使由栅电极13和半导体基板1的表面经由第二栅极绝缘膜10形成的单位电容器的值高于单位电容器的值，其通过第一栅极绝缘膜7由栅电极13和基板1的表面形成。作为用于膜7的氮化硅膜的电介质接触高于氧化硅膜的介电常数用于薄膜10时，容易获得上述两单元电容器尺寸之间的关系。

2. 发明公开

KR1020010014940A 반도체 장치 및 그 제조 방법 失效
标题翻译：半导体器件及其制造
公开(公告)号：KR1020010014940A
公开(公告)日：2001-02-26
申请号：KR1020000026939
申请日：2000-05-19
申请人： 미쓰비시덴키 가부시키가이샤
发明人： 구로이다까시 , 이또야스요시 , 호리따가쯔유끼 , 시오자와가쯔오미
IPC分类号： H01L29/78
CPC分类号： H01L29/66553 , H01L21/26586 , H01L21/28088 , H01L21/28114 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： PURPOSE: To provide a semiconductor device, the operation speed of which can be increased by reducing the channel length without increasing the gate resistance, and a method for manufacturing the device. CONSTITUTION: An MOSFET is provided with a groove type element isolation structure 2 formed in the main surface of a semiconductor substrate 1, a pair of extensions 3 and source and drain regions 4 both of which are selectively formed in the main surface of the substrate 1 and faced opposite to each other on both sides of a channel region 50, and silicon oxide films 5 formed on the source and drain regions 4 via the element isolation structure 2 and silicon oxide film 12. The MOSFET is also provided with sidewalls 6 formed on the side faces of the silicon oxide films 5, a gate insulating film 7 formed on the main surface of the substrate 1 in the portion where the cannel area 50 is formed, and a gate electrode 8 which is formed so as to fill up the inversely tapered recessed section formed of the side faces of the sidewalls 6 and upper surface of the gate insulating film 7.
摘要翻译：目的：提供一种半导体器件，其操作速度可以通过减小沟道长度而不增加栅极电阻而增加，以及制造器件的方法。构成：MOSFET设置有形成在半导体基板1的主表面中的沟槽型元件隔离结构2，一对延伸部3和源极和漏极区域4，它们都被选择性地形成在基板1的主表面中并且在沟道区域50的两侧彼此相对地形成，以及通过元件隔离结构2和氧化硅膜12在源极和漏极区域4上形成的氧化硅膜5.MOSFET还设置有形成在氧化硅膜5的侧面，在形成有槽区域50的部分形成在基板1的主面上的栅极绝缘膜7，以及形成为反向填充的栅电极8 由侧壁6的侧面和栅极绝缘膜7的上表面形成的锥形凹部。

3. 发明授权

KR100395721B1 반도체 장치의 제조 방법 失效
标题翻译： 반도체장치의제조방법
公开(公告)号：KR100395721B1
公开(公告)日：2003-08-25
申请号：KR1020010060375
申请日：2001-09-28
申请人： 미쓰비시덴키 가부시키가이샤
发明人： 시오자와가쯔오미 , 구로이다까시 , 호리따가쯔유끼
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/76235
摘要： A method of manufacturing a semiconductor device is provided which, even if device dimensions decrease, prevents degradation in the operating characteristics of semiconductor elements which are isolated from each other by an element isolation region in a trench isolation structure. Implantation of ions (15) in a polycrystalline silicon layer (3) from above through a silicon nitride film (2) produces an ion-implanted polycrystalline silicon layer (16). Since the ions (15) are an ionic species of element which acts to enhance oxidation, the implantation of the ions (15) changes the polycrystalline silicon layer (3) into the ion-implanted polycrystalline silicon layer (16) having a higher oxidation rate. In subsequent formation of a thermal oxide film (21) on the inner wall of a trench (5), exposed part of the ion-implanted polycrystalline silicon layer (16) is also oxidized, forming relatively wide polycrystalline silicon oxide areas (21a).
摘要翻译：提供了一种制造半导体器件的方法，即使器件尺寸减小，也可以防止由沟槽隔离结构中的元件隔离区彼此隔离的半导体元件的工作特性的劣化。从上方通过氮化硅膜（2）在多晶硅层（3）中注入离子（15）产生离子注入多晶硅层（16）。由于离子（15）是用于增强氧化作用的元素的离子种类，所以离子（15）的注入将多晶硅层（3）改变为具有较高氧化速率的离子注入多晶硅层（16）。在随后在沟槽（5）的内壁上形成热氧化膜（21）时，离子注入的多晶硅层（16）的暴露部分也被氧化，形成相对宽的多晶氧化硅区域（21a）。

4. 发明公开

KR1020020027161A 반도체 장치 및 반도체 장치의 제조 방법 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020020027161A
公开(公告)日：2002-04-13
申请号：KR1020010032296
申请日：2001-06-09
申请人： 미쓰비시덴키 가부시키가이샤
发明人： 구로이다까시 , 우에노슈이찌 , 호리따가쯔유끼
IPC分类号： H01L21/762
CPC分类号： H01L21/823481 , H01L21/76235 , H01L29/1033
摘要： PURPOSE: A semiconductor device and a manufacturing method thereof are provided to reduce the formation of parasitic in an active region and enable a semiconductor device to operate in a desired way. CONSTITUTION: A trench(2) is formed in a substrate(1) and a silicon oxide film(9) which serves as a trench isolation is buried in the trench(2). The silicon oxide film(9) has no shape sagging from a main surface(1S) of the substrate(1). A channel impurity layer(10) to control a threshold voltage of a MOSFET is formed in the main surface(1S) of the substrate(1). The channel impurity layer(10) is made of P-type layer, having an impurity concentration higher than that of the substrate(1). A first portion(10A) of the channel impurity layer(10) is formed near an opening edge of the trench(2) along a side surface of the trench(2) in the source/drain layer, and more specifically, in the N+-type layer. A second portion(10B) of the channel impurity layer(10) is formed deeper than the first portion(10A). A gate insulating film(4) and a gate electrode(5) are formed on the main surface(1S) of the substrate(1).
摘要翻译：目的：提供一种半导体器件及其制造方法，以减少有源区域中寄生的形成，并使半导体器件以期望的方式工作。构成：在衬底（1）中形成沟槽（2），并且用作沟槽隔离的氧化硅膜（9）被埋在沟槽（2）中。氧化硅膜（9）没有从基板（1）的主表面（1S）下垂的形状。在衬底（1）的主表面（1S）中形成用于控制MOSFET的阈值电压的沟道杂质层（10）。沟道杂质层（10）由杂质浓度高于衬底（1）的P型层制成。沟道杂质层（10）的第一部分（10A）沿着沟槽（2）的源极/漏极层的侧表面在沟槽（2）的开口边缘附近形成，更具体地，在N + 型层。沟道杂质层（10）的第二部分（10B）形成得比第一部分（10A）更深。在基板（1）的主表面（1S）上形成栅极绝缘膜（4）和栅电极（5）。

5. 发明授权

KR100283021B1 트렌치형 소자분리 구조의 제조방법 有权
标题翻译：沟槽式器件隔离结构的制造方法
公开(公告)号：KR100283021B1
公开(公告)日：2001-04-02
申请号：KR1019970079096
申请日：1997-12-30
申请人： 미쓰비시덴키 가부시키가이샤
发明人： 호리따가쯔유끼 , 구로이다까시 , 사까이마이꼬
IPC分类号： H01L21/76
摘要： 본 발명은 트렌치형 소자 분리의 매립 산화막의 에지(edge)부에서 오목부가 발생하지 않는 트렌치형 소자 분리 구조의 제조 방법을 제공한다.
실리콘 기판에 형성된 홈 내부의 매립 산화막의 주위뿐만 아니라, 실리콘 기판 표면으로부터 상부로 돌출된 매립 산화막의 측면에도 CVD막보다 내에칭성이 높은 열산화막을 형성한다.

6. 发明授权

KR100272987B1 반도체장치및그제조방법 失效
标题翻译：半导体器件及其制备方法
公开(公告)号：KR100272987B1
公开(公告)日：2000-12-01
申请号：KR1019980007246
申请日：1998-03-05
申请人： 미쓰비시덴키 가부시키가이샤
发明人： 사까이마이꼬 , 구로이다까시 , 호리따가쯔유끼
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： 본 발명의 목적은 양호한 전기 특성의 홈형 소자 분리 영역을 얻는데 있다. 본 발명에 따른 반도체 장치는 홈형의 소자 분리 영역을 테이퍼각 A1, A2, A3을 구성하여 굴곡하는 측벽을 갖고, 이 측벽이 반도체 기판의 표면에 평행한 위치 관계에 있는 저면을 갖는 홈의 내부에 형성되고, 테이퍼각 A1, A2, A3이 A1

7. 发明公开

KR1019980079356A 반도체장치및그제조방법 失效
公开(公告)号：KR1019980079356A
公开(公告)日：1998-11-25
申请号：KR1019970046491
申请日：1997-09-10
申请人： 미쓰비시덴키 가부시키가이샤
发明人： 호리따가쯔유끼 , 구로이다까시 , 오꾸무라요시노리
IPC分类号： H01L29/78
摘要： 소스/드레인 영역의 고저항화를 방지하여 고속이고, 또 안정한 동작을 하는 고수율의 반도체 장치를 얻음과 동시에, 그와 같은 반도체 장치의 제조 방법을 얻는다.
제1 저농도 불순물 영역(5)의 상부에 있어 사이드월 절연체(6y) 바로 아래 부분 이외의 부분에 홈부(8)를 형성하여 사이드월 절연체(6y) 형성시의 대미지층을 제거함과 동시에, 상기 홈부(8)의 하부에 제2 저농도 불순물 영역(10)을 형성한다.

8. 发明授权

KR100386939B1 반도체 장치 및 그 제조 방법 失效
标题翻译： 반도체장치및그제조방법
公开(公告)号：KR100386939B1
公开(公告)日：2003-06-09
申请号：KR1020000062580
申请日：2000-10-24
申请人： 미쓰비시덴키 가부시키가이샤
发明人： 구로이다까시 , 호리따가쯔유끼 , 우에노슈이찌 , 시오자와가쯔오미
IPC分类号： H01L29/78
摘要： PROBLEM TO BE SOLVED: To realize a MOSFET, which can increase its on-current and can reduce its off-current, by a method, where the threshold voltage of the ends of a channel region is made low in comparison with the threshold voltage of the center of the channel region. SOLUTION: In a MOSFET 201, the value of a unit capacitor, which is formed by a gate electrode 13 and the surface of a semiconductor substrate 1 via a second gate insulating film 10, can be made higher than that value of a unit capacitor, which is formed by the gate electrode 13 and the surface of the substrate 1 via first gate insulating films 7. As the dielectric contact of a silicon nitride film, which is used for films 7, is higher than the dielectric constant of a silicon oxide film, which is used for the film 10, it is easy to obtain this relation between the sized of the above two-unit capacitors.
摘要翻译：要解决的问题：为了实现能够增加其导通电流并且能够减小其截止电流的MOSFET，通过一种方法，其中沟道区域的端部的阈值电压与阈值电压频道区域的中心。解决方案：在MOSFET 201中，可以使由栅电极13和半导体衬底1的表面经由第二栅极绝缘膜10形成的单位电容器的值高于单位电容器的值，它由栅电极13和衬底1的表面通过第一栅极绝缘膜7形成。由于用于膜7的氮化硅膜的电介质接触高于氧化硅膜的介电常数，用于薄膜10时，容易获得上述两个单元电容器尺寸之间的这种关系。

9. 发明授权

KR100385764B1 반도체 장치 및 그 제조 방법 失效
标题翻译： 반도체장치및그제조방법
公开(公告)号：KR100385764B1
公开(公告)日：2003-05-28
申请号：KR1020010032303
申请日：2001-06-09
申请人： 미쓰비시덴키 가부시키가이샤
发明人： 우에노슈우이찌 , 호리따가쯔유끼 , 구로이다까시
IPC分类号： H01L29/78
CPC分类号： H01L29/1083 , H01L21/26586 , H01L27/10808 , H01L27/10829 , H01L27/10841 , H01L27/10873 , H01L29/1045 , H01L29/105 , H01L29/66537 , H01L29/66545 , H01L29/7836
摘要： Provided are a semiconductor device having a MOS transistor of a structure capable of obtaining a good characteristic particularly about assurance of resistance to punch-through and leak current reduction, as well as a method of manufacturing the same. That is, in addition to the usual MOS transistor structure, a channel dope region (1) is disposed at a predetermined depth so as to extend substantially the entire surface of a flat surface in a P well region (22) including a channel region. In the channel dope region (1), it is set so that the maximum value of the P type impurity concentration (MAX of P) ranges from 1x1018 to 1x1019, and the maximum value of the N type impurity concentration (MAX of N) of a source/drain region (31 (32)) is not less than 10% and not more than 100%. Note that the surface proximate region of the P well region (22) is to be beyond the object.
摘要翻译：本发明提供一种半导体器件及其制造方法，该半导体器件具有能够获得良好特性的结构的MOS晶体管，特别是关于确保耐穿透性和泄漏电流降低的半导体器件。即，除了通常的MOS晶体管结构之外，沟道掺杂区（1）以预定的深度布置，以便在包括沟道区的P阱区（22）中的平坦表面的基本上整个表面上延伸。在沟道掺杂区（1）中，P型杂质浓度（P的MAX）的最大值在1×1018〜1×1019的范围内设定，N型杂质浓度（N的MAX）的最大值源极/漏极区域（31（32））不小于10％且不大于100％。请注意，P阱区（22）的表面附近区域将超出物体。

10. 发明授权

KR100378839B1 반도체 장치 및 그 제조 방법 失效
标题翻译： 반도체장치및그제조방법
公开(公告)号：KR100378839B1
公开(公告)日：2003-04-07
申请号：KR1020000026939
申请日：2000-05-19
申请人： 미쓰비시덴키 가부시키가이샤
发明人： 구로이다까시 , 이또야스요시 , 호리따가쯔유끼 , 시오자와가쯔오미
IPC分类号： H01L29/78
CPC分类号： H01L29/66553 , H01L21/26586 , H01L21/28088 , H01L21/28114 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： An object is to obtain a semiconductor device in which channel length is reduced without increasing the gate resistance to realize higher operation speed and its manufacturing method. An MOSFET has a trench-type element isolation structure ( 2 ) formed in the main surface of a semiconductor substrate ( 1 ), a pair of extensions ( 3 ) and source/drain regions ( 4 ) selectively formed in the main surface of the semiconductor substrate ( 1 ) to face each other through a channel region ( 50 ), a silicon oxide film ( 5 ) formed on the trench-type element isolation structure ( 2 ) and on the source/drain regions ( 4 ) through a silicon oxide film ( 12 ), sidewalls ( 6 ) formed on sides of the silicon oxide film ( 5 ), a gate insulating film ( 7 ) formed on the main surface of the semiconductor substrate ( 1 ) in the part in which the channel region ( 50 ) is formed, and a gate electrode ( 8 ) formed to fill a recessed portion in an inversely tapered form formed by the sides of the sidewalls ( 6 ) and the upper surface of the gate insulating film ( 7 ).
摘要翻译：本发明的目的是获得一种半导体器件，其中沟道长度减小而不增加栅极电阻以实现更高的工作速度及其制造方法。 MOSFET具有形成在半导体衬底（1）的主表面中的沟槽型元件隔离结构（2），在半导体衬底（1）的主表面中选择性形成的一对延伸部（3）和源极/漏极区（4）衬底（1）通过沟道区（50），形成在沟槽型元件隔离结构（2）上和源极/漏极区（4）上的氧化硅膜（5）通过氧化硅膜（1）的主表面上形成的栅极绝缘膜（7），在沟道区（50）的部分上形成的栅极绝缘膜（7），形成在氧化硅膜（5）的侧面上的侧壁（6）以及形成为以由侧壁（6）的侧面和栅极绝缘膜（7）的上表面形成的倒锥形形式填充凹部的栅电极（8）。

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