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1. 发明专利

JP3717941B2 Signal reception dexterity slice predictor 失效
公开(公告)号：JP3717941B2
公开(公告)日：2005-11-16
申请号：JP53546097
申请日：1997-03-31
申请人：ゼニス、エレクトロニクス、コーポレーション
发明人：エイ．ウィルミング，デイビッド
IPC分类号： H04L27/38 , H03M13/23 , H04L25/03 , H04L25/08 , H04L25/34 , H04L27/06
CPC分类号： H04L25/03273 , H04L25/03324 , H04L2025/03382

2. 发明专利

JP2002525977A 失效
公开(公告)号：JP2002525977A
公开(公告)日：2002-08-13
申请号：JP2000571616
申请日：1999-09-20
IPC分类号： H04L25/03 , H03K17/16 , H03M1/66 , H04B1/62 , H04B3/00 , H04B3/04 , H04L23/02 , H04L25/34 , H04L27/00 , H04L27/04
摘要： The present invention overcomes ISI by precompensating for the anticipated high-frequency energy losses in the transmission media. This precompensation is accomplished using a preemphasis waveform, i.e., driving the differential signal to a value larger than normal on a signal edge. Preemphasis increases the slew rate of edges inside data with a lot of transitions relative to data with fewer transitions, thereby compensating for the low-pass effects of the transmission cable. The present invention further contemplates adaptive control for ensuring that varying operating conditions do not effect preemphasis waveform generation. The first approach involves tracking the operation of a replicate driver for each main driver and adaptively controlling each main driver depending upon feedback from the replicate driver. A second approach, that is both more complicated and more effective, involves measuring the signal and the line impedance at the output of the main driver and adaptively controlling the main driver in response.

3. 发明专利

JPH08204760A BIPOLAR CLOCK DISTURBANCE DETECTION CIRCUIT 失效
公开(公告)号：JPH08204760A
公开(公告)日：1996-08-09
申请号：JP1160195
申请日：1995-01-27
申请人： NEC CORP
发明人： TAKAHASHI YASUNORI
IPC分类号： H04L25/49 , G06F1/04 , H03K5/19 , H04L7/00 , H04L7/08 , H04L25/02 , H04L25/34
摘要： PURPOSE: To realize a bipolar clock disturbance detection circuit in which the disturbance of a bipolar clock is surely detected. CONSTITUTION: A bipolar clock disturbance detection circuit is made up of a unipolar signal extract means 1, a 1st abnormality discrimination means 3, a 2nd abnormality discrimination means 5, and an OR circuit 7. A pulse detection circuit 11 of the extract means 1 extracts a positive polarity pulse S1 from a bipolar clock BCL and a pulse detection circuit 12 extracts a negative polarity pulse S2. The abnormality discrimination means 3 allows a register 32 to shift frequency division data S3 of the pulse S1 by a frequency dividing circuit 31 by using the pulse S2 as a clock and discriminates it to be an error when the shifted result differs from a predetermined value. An abnormality discrimination means 5 allows a register 52 to shift the frequency division data S4 of the pulse S2 by a frequency divider circuit 51 by using the pulse S1 as a clock and discriminates it to be an error when the shifted result differs from a predetermined value.

4. 发明专利

JPH077527A DIGITAL MANY-VALUED SYMBOL TRANSMISSION SYSTEM 失效
公开(公告)号：JPH077527A
公开(公告)日：1995-01-10
申请号：JP3742594
申请日：1994-03-08
申请人： KONINKL PHILIPS ELECTRONICS NV
发明人： FISHER KEVIN DEAN , WONG-LAM HO WAI , BERGMANS JOHANNES WILHELMUS M , STEENHOF FRITS ANTHONY , VOORMAN JOHANNES
IPC分类号： H04L25/03 , H03K5/08 , H03M13/23 , H04L25/06 , H04L25/12 , H04L25/30 , H04L25/34 , H04L25/49 , H03M13/12
摘要： PURPOSE: To reduce the occurrence of errors by making the ratio of the amplitude of a detected signal to a reference value to an appropriate value adaptive based on the combination of an adaptive signal and a correct signal to always guide the ratio. CONSTITUTION: A quinary digital signal ak from a transmitter 2 is inputted to a detecting means 14 and an adaptive means 16 through the leading-out means 8 of a receiver 6. The destination signal output ak of the detecting means 14 is inputted to a correcting means 19 through a monitor 18 and a correction signal obtained by comparing the output ak with a reference value is inputted to an adding circuit 20. On the other hand, the adaptive means 16 adaptively decides an amplitude transfer function from a value related to the output rk of the AGC amplifier 12 of the leading-out means 8, inputs the function to the adding circuit 20, and controls the amplifier 12 with a value integrated by means of an integrator 22 by coupling the function with the correction signal. Therefore, the occurrence of symbol errors can be suppressed, because the ratio of a detected signal to the reference value can always be adjusted to an appropriate value.

5. 发明专利

JPS61280146A TERNARY SIGNAL SAMPLING CIRCUIT 失效
公开(公告)号：JPS61280146A
公开(公告)日：1986-12-10
申请号：JP12383986
申请日：1986-05-30
申请人： PHILIPS NV
发明人： LOSCHER JUERGEN
IPC分类号： H04L25/40 , H03K5/156 , H03M5/16 , H04L7/02 , H04L25/08 , H04L25/24 , H04L25/34

6. 实用新型

JPS60167443U 失效
公开(公告)号：JPS60167443U
公开(公告)日：1985-11-07
申请号：JP5454484
申请日：1984-04-13
IPC分类号： H03M5/04 , H03K5/00 , H04L25/03 , H04L25/34 , H04L25/49

7. 发明专利

JPS58195339A Signal transmitting device 失效
标题翻译：信号发送装置
公开(公告)号：JPS58195339A
公开(公告)日：1983-11-14
申请号：JP7947182
申请日：1982-05-10
申请人： Mitsubishi Electric Corp
发明人： YOSHIZAKI AKITOSHI , HAYASHI SHINICHIROU
IPC分类号： H04L25/34 , H04L7/04 , H04L25/03 , H04L25/49 , H04L25/493
CPC分类号： H04L25/493
摘要： PURPOSE:To improve noise resistance, by receiving the 1st and the 2nd pulses having different synchornizing ''1'' level of front and tail ridges of a transmission signal and extracting a pulse signal within a permissible level range at the reception side. CONSTITUTION:A conversion circuit 11 generates pulses P11, P12 which are in synchornization with the front and tail ridges of the transmission signal P and transmits pulses P100 and P50 of levels 2E and E. When the pulse P100 is received, diodes 403, 503 and 504 having
摘要翻译：目的：通过接收传输信号的前，后脊的同步“1”电平的第1和第2脉冲，并在接收侧提取允许电平范围内的脉冲信号，提高抗噪性。变换电路11产生与发送信号P的前，后脊同步的脉冲P11，P12，并发送电平2E，E的脉冲P100，P50。当接收到脉冲P100时，二极管403,503和具有齐纳电势的<= EV的导电性，双稳态多谐振荡器600产生输出。另一方面，TR 501被关断，并且没有输入给双稳态多谐振荡器600.当接收到脉冲P50时，它仅仅通过齐纳二极管503，仅使TR 502导通，并且输出双稳态多谐振荡器600分散。因此，从双稳态多谐振荡器600提取信号P.当接收脉冲高于二极管404的齐纳二极管时，双稳态多谐振荡器600不产生输出。当接收脉冲的电平低于二极管504的齐纳电位时，所有齐纳二极管都被切断。

8. 发明专利

JPS585062A INTERCHIP TRANSMITTER FOR LOGIC SIGNAL 失效
公开(公告)号：JPS585062A
公开(公告)日：1983-01-12
申请号：JP8410482
申请日：1982-05-20
申请人： IBM
发明人： ARUMAN BURIYUNAN , GI DERUBII
IPC分类号： H04L25/02 , H03K19/003 , H03K19/0175 , H03K19/018 , H03K19/21 , H03K19/23 , H04L25/08 , H04L25/12 , H04L25/34

9. 发明专利

JPS57176443A SYSTEM HAVING FIRST AND SECOND ACTIVE FUNCTION UNIT 失效
公开(公告)号：JPS57176443A
公开(公告)日：1982-10-29
申请号：JP5481082
申请日：1982-04-03
申请人： PHILIPS NV
发明人： KARERU SUTEBUEN SHIYORUTEN , ARIE SUROBU , PIERE HERARUDASU YANSEN
IPC分类号： G06F13/42 , H04L7/00 , H04L25/34 , H04L29/08

10. 发明专利

JPS5136162B2 失效
公开(公告)号：JPS5136162B2
公开(公告)日：1976-10-07
申请号：JP6882872
申请日：1972-07-10
IPC分类号： H04L27/34 , H04L25/34 , H04L27/02 , H04N1/00 , H04N1/41

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