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1. 发明专利

JP3674850B2 Phase lock loop circuit having an automatic adjusting function of the free-running frequency of the voltage controlled oscillator 有权
公开(公告)号：JP3674850B2
公开(公告)日：2005-07-27
申请号：JP2001376964
申请日：2001-12-11
申请人：ソニー株式会社
发明人：哲也下田
IPC分类号： G09G3/20 , H03L7/085 , H03L7/10 , H03L7/113 , H03L7/189
CPC分类号： H03L7/085 , H03L7/10 , H03L7/189

2. 发明专利

JP2003318732A Semiconductor integrated circuit for communication, and radio communication system 审中-公开
标题翻译：用于通信的半导体集成电路和无线电通信系统
公开(公告)号：JP2003318732A
公开(公告)日：2003-11-07
申请号：JP2002125631
申请日：2002-04-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： OSAWA HIROTAKA , KASAHARA MASUMI , KURAGAMI NORIYUKI , UOZUMI TOSHIYA
IPC分类号： H03L7/187 , H03L7/089 , H03L7/099 , H03L7/10 , H03L7/183 , H03L7/189 , H03L7/193 , H04B1/3822 , H04B1/40
CPC分类号： H03L7/10 , H03L7/0891 , H03L7/193
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for communication (high-frequency IC), by which a PLL circuit can be brought into a desired set frequency at a high speed, without providing a current source separately from a current source for charging and discharging in normal operations, even when the range can be set is wide for the frequency of the PLL circuit. SOLUTION: An oscillation circuit (VCO 10) comprising the PLL circuit is constructed operably in several bands. A control voltage (Vc) of the oscillation circuit is fixed to a predetermined value (V DC), and oscillation frequency of the oscillation circuit in each of the bands is measured and stored in a storage circuit (18). A set value for specifying the band, given during the operation of the PLL and the measured frequency value which is stored in this way, are compared and the band to be actually used in the oscillation circuit is determined by the result of comparison. Also, the frequency difference between the maximum frequency of the selected band and the set frequency is found, and a control voltage which is closest to the set frequency is determined from the frequency difference ad the variable range of frequency of the selected band. The control voltage is applied to the oscillation circuit for starting its oscillation operations, and then a PLL loop is closed and locked. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了提供用于通信（高频IC）的半导体集成电路，通过该半导体集成电路，PLL电路可以以高速被带入期望的设定频率，而不与电流分开提供电流源即使在PLL电路的频率范围可以设定范围宽的情况下，也可以在正常动作中进行充放电。解决方案：包括PLL电路的振荡电路（VCO 10）可在几个频带中可操作地构造。将振荡电路的控制电压（Vc）固定为规定值（V DC），测定各频带的振荡电路的振荡频率并将其存储在存储电路（18）中。比较用于指定在PLL操作期间给出的频带的设定值和以这种方式存储的测量频率值，并且由比较结果确定在振荡电路中实际使用的频带。此外，找到所选频带的最大频率与设定频率之间的频率差，并且根据所选频带的频率的可变范围的频率差确定最接近设定频率的控制电压。将控制电压施加到振荡电路以开始其振荡操作，然后PLL环路闭合并锁定。版权所有（C）2004，JPO

3. 发明专利

JPH11191734A PLL CIRCUIT 失效
公开(公告)号：JPH11191734A
公开(公告)日：1999-07-13
申请号：JP28540598
申请日：1998-10-07
申请人： NEC CORP
发明人： TOLSON NIGEL JAMES
IPC分类号： H03L7/099 , H03L7/10 , H03L7/189
摘要： PROBLEM TO BE SOLVED: To omit every manual frequency regulation by operating an external controller to vary a voltage at the second input part of a voltage controlled oscillator(VCO) independently of a loop voltage impressed to the first input part of the oscillator. SOLUTION: A CPU 13 changes the frequency of a VCO 10 by applying a variable voltage to the anode of a varactor diode D1 as needed independently of the fluctuation of a voltage to reach a first input part 10a of the VCO 10 through a feedback loop. A loop filter voltage is sampled, a digital value expressing the DC voltage of a loop filter output is supplied to the CPU 13 by an A/D converter 16, and the CPU 13 compares this DC voltage with a voltage level desired for a prescribed channel and outputs a digital value corresponding to a regulated voltage. This output is impressed to a sample-and-hold circuit 17 and as a result, the regulated voltage is applied to the anode of the varactor diode D1.

4. 发明专利

JPH1056329A FREQUENCY CONTROL OSCILLATOR 失效
公开(公告)号：JPH1056329A
公开(公告)日：1998-02-24
申请号：JP21231196
申请日：1996-08-12
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： NOMURA YOSHINOBU , FUKUDA HIDEYUKI
IPC分类号： H03B1/00 , H03B5/12 , H03B5/32 , H03B5/36 , H03L1/02 , H03L7/099 , H03L7/189
摘要： PROBLEM TO BE SOLVED: To obtain an oscillator by which a wide variable frequency band width and sufficient frequency precision are simultaneously obtained and also which is easily controlled by providing plural input terminals for inputting the control signal of the frequency of an output signal. SOLUTION: The plural input terminals 7 and 8 are provided for inputting the control signal of the frequency of the output signal. In the oscillator, a transistor 2 is oscillated, the frequency of the signal to be outputted from a signal output terminal 9 is value-decided by a crystal vibrator 3 on the whole but an oscillation frequency is controlled from an external part by changing the capacitance of variable capacitance diodes 4 and 5 in accordance with voltages inputted from the input terminals 7 and 8. At this time, the sensitivity of the variable width of the frequency in the output signal as against the change width of the voltages to be inputted from the input terminals 7 and 8 is made different in the input terminal 7 and the input terminal 8 is not increased to extend the variable width of the frequency at the same resolution without increasing the number of bits in a D/A converter for deciding an inputted control signal voltage.

5. 发明专利

JPH1051303A PHASE LOCKED LOOP CIRCUIT 失效
公开(公告)号：JPH1051303A
公开(公告)日：1998-02-20
申请号：JP11694997
申请日：1997-05-07
申请人： LG SEMICON CO LTD
发明人： LEE YONG-WON
IPC分类号： H03L7/00 , H03L7/10 , H03L7/187 , H03L7/189
摘要： PROBLEM TO BE SOLVED: To quickly lock a frequency by generating a voltage pertinent to a channel frequency, comparing the size of the voltage with the size of the voltage outputted from a loop filter and deciding the voltage to be supplied to a voltage controlled oscillator(VCO) by the result. SOLUTION: A frequency/phase detector 1, the loop filter 2, a VCO control part 100 and the VCO 3 are closed-loop connected. The channel data of N bits (N is an optional natural number) by the channel frequency decided corresponding to an operated external system are converted and the signals of a prescribed level pertinent to the channel frequency are generated. The level of the generated signals and the level of the signals outputted from the loop filter 2 are compared, the output signals of the loop filter 2 are outputted when the levels are equal and the generated signals are outputted when the levels are different. Thus, the frequency is locked when feedback is performed for one time in a loop.

6. 发明专利

JPH09270704A PHASE LOCKED LOOP CIRCUIT 失效
公开(公告)号：JPH09270704A
公开(公告)日：1997-10-14
申请号：JP8020896
申请日：1996-04-02
申请人： TOSHIBA CORP
发明人： NAKAO TAKEHIKO , YOSHIOKA SHINICHI
IPC分类号： H03L7/113 , H03L7/10 , H03L7/189
摘要： PROBLEM TO BE SOLVED: To set a gain shared by an analog loop to relatively low by making a frequency of an internal signal close to a frequency of an input signal through digital control and matching the phases through analog control. SOLUTION: A digital control loop system sets stepwise an oscillated frequency of a VCO 36 in the initial lock process of a PLL loop to make a frequency of an internal signal outputted from the VCO 36 close to a frequency of an input signal (synchronized signal) to conduct digital oscillation frequency control. On the other hand, an analog control system controls continuously an oscillated frequency of the VCO 36 to lock the PLL loop into the lock state after the frequency of the internal signal is close to the vicinity of the frequency of the input signal.

7. 发明专利

JPH04506737A 失效
公开(公告)号：JPH04506737A
公开(公告)日：1992-11-19
申请号：JP50485091
申请日：1991-01-24
IPC分类号： H03L7/093 , H03C3/00 , H03C3/09 , H03L7/187 , H03L7/189

8. 发明专利

JPH02180431A SIGNAL GENERATOR 失效
公开(公告)号：JPH02180431A
公开(公告)日：1990-07-13
申请号：JP27959389
申请日：1989-10-26
申请人： HEWLETT PACKARD CO
发明人： IIRU SHII HAAREIKUSON
IPC分类号： H03L7/187 , H03C3/00 , H03C3/09 , H03L7/113 , H03L7/18 , H03L7/189 , H03L7/197
摘要： PURPOSE: To minimize the phase noise by including a frequency locked loop FLL consisting of a delay line discriminator to measure the FM noise of the output signal of a VCO, and to feedback a frequency control signal to a line. CONSTITUTION: A PLL and the FLL are combined by coupling the output of a PLL gain amplifier 19 of a line 18 to a frequency discriminator variable phase shift network 25, and a PLL tuning voltage derived from an error signal by a PLL phase detector adjusts the phase shift of the variable phase shift network 25 to compensate the change of the output frequency of a VCO 11. Since the variation in frequency of the output signal of the VCO 11 is corrected, a profit of a high loop gain of the FLL is obtained. Thus, precise phase coherency is presented to a reference frequency, and an FLL having a narrow band width can be used because the phase noise in a small frequency offset from a carrier frequency is reduced.

9. 发明专利

JPH02180430A FREQUENCY SYNTHESIZER 失效
公开(公告)号：JPH02180430A
公开(公告)日：1990-07-13
申请号：JP27959089
申请日：1989-10-26
申请人： HEWLETT PACKARD CO
发明人： JIYOOJI SUCHIIBUN KAACHISU
IPC分类号： H03L7/187 , H03B1/00 , H03C3/00 , H03C3/09 , H03C3/22 , H03L7/081 , H03L7/113 , H03L7/18 , H03L7/189 , H03L7/197
摘要： PURPOSE: To provide a low-noise, wide-band, and high-speed precise frequency synthesizer by effectively coupling a phase locked loop(PLL) to a frequency locked loop(FLL) and giving such constitution that a maximum operation point of the coupled loop may be kept. CONSTITUTION: The output of a VCO 11 is subjected to frequency division in an N frequency division block 13 by a selectable number N to generate an input signal to a PLL phase detector 15. This detector 15 compares this input signal with a prescribed reference signal to generate an error signal which has a voltage proportional to the phase difference, and a PLL tuning signal is given to the VCO 11 through a PLL filter 17 and a PLL gain amplifier 19. Further, the FLL including a delay line discriminator 10 which sends back a frequency control signal (VCO tuning signal) through a line 34 is included, and the output of the gain amplifier 19 is coupled to a variable phase network 25 of the frequency discriminator 10 by a line 18, and phase shift of the variable phase shift network 25 is adjusted by the PLL tuning voltage to compensate the change of the output frequency of the VCO 11.

10. 发明专利

JPH0224414B2 失效
公开(公告)号：JPH0224414B2
公开(公告)日：1990-05-29
申请号：JP4852182
申请日：1982-03-26
申请人： YAESU MUSEN KK
发明人： KAMEYAMA YOSHINORI
IPC分类号： H03L7/18 , H03L7/183 , H03L7/187 , H03L7/189

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