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1. 发明专利

KR20210028488A KR20210028488A - High efficiency current-reuse frequency quadrupler 审中-公开
公开(公告)号：KR20210028488A
公开(公告)日：2021-03-12
申请号：KR1020190109656A
申请日：2019-09-04
申请人： 국방과학연구소 , 한국과학기술원
发明人： 정우현 , 홍성철 , 김종필 , 김완식 , 정주용 , 이주영 , 서미희 , 김소수
IPC分类号： H03B19/10 , H03B19/14
CPC分类号： H03B19/10 , H03B19/14
摘要： 본 발명은, 전류 재사용 주파수 4배 체배기에 관한 것으로, 입력된 신호에서 기본 주파수의 2배 주파수를 체배하는 제1모듈, 상기 제1 모듈에서 체배된 신호를 입력받아 위상이 반대인 신호를 출력하는 제2모듈 및 상기 제1모듈 및 제2모듈과 연결되고, 상기 제1모듈 및 상기 제2모듈로부터 입력된 신호를 기반으로, 상기 기본 주파수의 4배 주파수를 체배하는 제3모듈을 포함하고, 상기 제1 , 제2 및 제3 모듈은, C등급(Class C) 트랜지스터를 포함하는 것을 특징으로 한다.

2. 发明专利

JP5597998B2 High-frequency double-wave oscillator 有权
公开(公告)号：JP5597998B2
公开(公告)日：2014-10-01
申请号：JP2010007092
申请日：2010-01-15
申请人：三菱電機株式会社
发明人：伸介渡辺 , 良洋塚原 , 康金谷 , 真一三輪
IPC分类号： H03B5/18 , H03B19/10
CPC分类号： H03B5/1847 , H03D2200/0086

3. 发明专利

JP2009278150A Voltage controlled oscillator 审中-公开
标题翻译：电压控制振荡器
公开(公告)号：JP2009278150A
公开(公告)日：2009-11-26
申请号：JP2008124546
申请日：2008-05-12
申请人： Alps Electric Co Ltd , アルプス電気株式会社
发明人： NAKATSUKA KENJI
IPC分类号： H03L7/099 , H03B5/02 , H03B19/10
CPC分类号： H03J3/26 , H03B19/00 , H03J3/185 , H03L7/099 , H03L2207/10
摘要： PROBLEM TO BE SOLVED: To secure high C/N and stability in frequency, to suppress a leakage of an unnecessary signal outside a band even when a frequency variable width gets wider and to achieve impedance matching at the same time. SOLUTION: A voltage controlled oscillator includes: a voltage controlled oscillation circuit 1, an oscillation frequency thereof being controlled by a control voltage signal; a PLL circuit 2 that generates a control voltage signal to be input to the voltage controlled oscillation circuit 1; a multiplier circuit 3 that multiplies an oscillation signal output from the voltage controlled oscillation circuit 1; and a band-pass filter and trap circuit 4 that sets a pass band for passing a signal with a predetermined multiplication number of multiplication signals output from the multiplier circuit 3 and a trap frequency to trap a frequency equal to the frequency of the oscillation signal input to the multiplier circuit 3. The control voltage signal is branched and input to an inter-stage coupling and trap circuit 15 to vary the pass band and the trap frequency of the inter-stage coupling and trap circuit 15 in synchronization with the control voltage signal, and also to adjust inter-stage coupling. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题为了确保高C / N和频率的稳定性，即使当频率可变宽度变宽并且同时实现阻抗匹配时，也可以抑制频带外的不必要信号的泄漏。压控振荡器包括：压控振荡电路1，其振荡频率由控制电压信号控制; 产生要输入到压控振荡电路1的控制电压信号的PLL电路2; 乘法电路3，其将从压控振荡电路1输出的振荡信号相乘; 以及带通滤波器和陷波电路4，其设置用于通过具有从乘法器电路3输出的预定倍数的乘法信号的信号的通带和陷波频率，以捕获与振荡信号输入的频率相等的频率控制电压信号被分支并输入到级间耦合和陷波电路15，以与控制电压信号同步地改变级间耦合和陷波电路15的通带和陷波频率，并且还调整级间耦合。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2009100131A Arbitrary waveform generator 审中-公开
标题翻译：仲裁波形发生器
公开(公告)号：JP2009100131A
公开(公告)日：2009-05-07
申请号：JP2007268264
申请日：2007-10-15
申请人： Yokogawa Electric Corp , 横河電機株式会社
发明人： ANAZAWA KYOJI
IPC分类号： H03B28/00 , H03B19/10 , H03M1/66
摘要： PROBLEM TO BE SOLVED: To provide an arbitrary waveform generator capable of increasing the band width of a sinusoid output frequency with a simple configuration.
SOLUTION: The arbitrary waveform generator wherein a waveform generated from a DA converter 1 synchronously with a clock signal on the basis of waveform data has the level adjusted by an output circuit 2, includes a waveform shaping circuit 4 for shaping the clock signal into a sinusoid and a first changeover switch 5 for switching an output signal of the waveform shaping circuit 4 or the DA converter 1 to the output circuit 2.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供能够以简单的配置增加正弦输出频率的带宽的任意波形发生器。解决方案：根据波形数据与DA转换器1产生的与时钟信号同步的波形的任意波形发生器具有由输出电路2调整的电平的波形整形电路4，用于对时钟信号进行整形成为正弦曲线和第一转换开关5，用于将波形整形电路4或DA转换器1的输出信号切换到输出电路2.版权所有（C）2009，JPO＆INPIT

5. 发明专利

JPS51105257A 失效
公开(公告)号：JPS51105257A
公开(公告)日：1976-09-17
申请号：JP2949275
申请日：1975-03-13
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： NAGAFUNE KAZUO , TOKIZAWA IKUO
IPC分类号： H03B19/20 , H03B19/06 , H03B19/10 , H03K3/33 , H03K12/00

6. 发明专利

JP2009290867A System and method for synthesizing signal 审中-公开
标题翻译：用于合成信号的系统和方法
公开(公告)号：JP2009290867A
公开(公告)日：2009-12-10
申请号：JP2009123137
申请日：2009-05-21
申请人： Honeywell Internatl Inc , ハネウェル・インターナショナル・インコーポレーテッド
发明人： TRINKLE WILLIAM JOSEPH
IPC分类号： H03B28/00 , H03B19/10 , H03B21/00 , H03M1/66
CPC分类号： G06F1/025 , H03K4/026
摘要： PROBLEM TO BE SOLVED: To provide a system and method for synthesizing a signal from odd-order harmonic frequency components of an input signal.
SOLUTION: An embodiment synthesizes a first signal using a digital-analog converter (DAC) 102, generates a second signal from the first signal, and filters the selected one of the odd-order harmonic frequency components through a band-pass filter 108 to generate an output signal. The first signal is determined by a first frequency. The second signal is determined by the first frequency, and includes a fundamental frequency component and a plurality of odd-order harmonic frequency components. The output signal has the frequency substantially equal to the selected frequency of the odd-order harmonic frequency components. A step of passing the selected one of the odd-order harmonic frequency components further includes the steps of: passing a third-hermonic frequency component through the band-pass filter; and generating the output signal from the passed third-hermonic frequency component.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于合成来自输入信号的奇次谐波频率分量的信号的系统和方法。解决方案：实施例使用数模转换器（DAC）102合成第一信号，从第一信号产生第二信号，并且通过带通滤波器对所选择的一个奇次谐波频率分量进行滤波 108以产生输出信号。第一信号由第一频率确定。第二信号由第一频率确定，并且包括基频分量和多个奇次谐波频率分量。输出信号的频率基本上等于奇次谐波频率分量的选定频率。使所选择的一个奇次谐波频率分量通过的步骤进一步包括以下步骤：使第三奇异频率分量通过带通滤波器; 以及从所述经过的第三 - 赫尔蒙特频率分量产生输出信号。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP4180479B2 Frequency multiplier, output buffer, semiconductor device, and the multiplication method of the clock frequency of the semiconductor device 有权
公开(公告)号：JP4180479B2
公开(公告)日：2008-11-12
申请号：JP2003330474
申请日：2003-09-22
申请人：三星電子株式会社Samsung Electronics Co.,Ltd.
发明人：賢淳張 , 敬桓権 , 圭現金
IPC分类号： G06F1/04 , H03K5/00 , G11C11/40 , G11C29/00 , G11C29/12 , H03B1/00 , H03B19/00 , H03B19/10 , H03K5/1534 , H03K21/10
CPC分类号： H03K5/1534 , H03K5/00006

8. 发明专利

JP2004328670A Highly stable oscillator 审中-公开
公开(公告)号：JP2004328670A
公开(公告)日：2004-11-18
申请号：JP2003124302
申请日：2003-04-28
申请人： Sumitomo Electric Ind Ltd , 住友電気工業株式会社
发明人： FUJII SATORU , ITAKURA KATSUHIRO
IPC分类号： H03B5/32 , H03B5/02 , H03B19/10
摘要： PROBLEM TO BE SOLVED: To provide a highly stable oscillator which easily provides a high-frequency oscillator having stable oscillation characteristics at low cost.
SOLUTION: An oscillator 1 is composed of a voltage controlled crystal oscillator (VCXO) which is a pre-stage low-frequency oscillator and generates and outputs a signal of 19.44 MHz, and a multiplication circuit 11 for multiplying by 32 a frequency of the signal from the VCXO to generate a high-frequency signal of 622.08 MHz, and a SAW filter 12 is installed on the post-stage of the multiplication circuit 11. The SAW filter 12 cuts an excessive frequency component by defining a frequency within a predetermined range from the frequency of 622.08 MHz in the multiplication circuit 11 as a central frequency and passing and outputting a signal component within the predetermined frequency range. Thus, the highly stable oscillator 1 wherein jitter is reduced, can be obtained.
COPYRIGHT: (C)2005,JPO&NCIPI

9. 发明专利

JP2004320413A Spurious suppression high frequency oscillation circuit 审中-公开
公开(公告)号：JP2004320413A
公开(公告)日：2004-11-11
申请号：JP2003111155
申请日：2003-04-16
申请人： Toyo Commun Equip Co Ltd , 東洋通信機株式会社
发明人： NOMURA NORIO
IPC分类号： H03B1/04 , H03B5/02 , H03B5/32 , H03B19/00 , H03B19/10
摘要： PROBLEM TO BE SOLVED: To provide a high frequency oscillator which is not affected by the changes of the stray capacitance and load capacitance of a board and hence the spurious characteristic of which is not deteriorated when impedance matching with the output terminal side is carried out in a VCXO adopting the multiplication system.
SOLUTION: Impedance matching with the output terminal side is carried out with high accuracy by inserting an attenuator comprising only resistive elements to an output section to suppress deterioration in the spurious characteristics.
COPYRIGHT: (C)2005,JPO&NCIPI

10. 发明专利

JP3382131B2 Pll circuit 失效
公开(公告)号：JP3382131B2
公开(公告)日：2003-03-04
申请号：JP20006797
申请日：1997-07-25
申请人：株式会社東芝
发明人：秋彦吉沢
IPC分类号： H03L7/08 , H03B19/10

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