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    • 1. 发明专利
    • Digital filter apparatus
    • 数码过滤器
    • JP2008099182A
    • 2008-04-24
    • JP2006281503
    • 2006-10-16
    • Toshiba CorpToshiba Microelectronics Corp東芝マイクロエレクトロニクス株式会社株式会社東芝
    • SUZUKI YASUYUKINAKAMURA SHINICHISATO HIROSHI
    • H03H17/04H03H17/02H03H17/06
    • H03H17/0294H03H2017/0295
    • PROBLEM TO BE SOLVED: To provide a digital filter apparatus capable of suppressing the noise that can be generated, when filter characteristics are to be changed.
      SOLUTION: In the digital filter apparatus 100, a peak value control circuit 8 compares a first gain multiplication value g0 with a second gain multiplication value, substitutes the filter coefficient for a new filter coefficient from a second coefficient register 7 and it is made to be stored in a first coefficient register 2 with the timing where timing the gain multiplication value becomes zero, or becomes closest to zero for the first time, and substitutes the filter coefficient for a new filter from the second coefficient register 7 and it is made to be stored in the first coefficient register 2 with the timing where the timing the closer of the first gain multiplication value and the second gain multiplication is applied to a gain multiplier 4, when the code of the first gain multiplication value is the same as that of the code of the second gain multiplication value. A IIR-type digital filter 3 uses the filter coefficient, stored in the first coefficient register 2, for filtering.
      COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题:提供一种能够抑制可能产生的噪声的数字滤波器装置,当要改变滤波器特性时。 解决方案:在数字滤波器装置100中,峰值控制电路8将第一增益乘法值g0与第二增益乘法值进行比较,将来自第二系数寄存器7的滤波器系数代入新的滤波器系数, 使其被存储在第一系数寄存器2中,其中增益倍数值的定时变为零的定时,或者第一次变为最接近零的定时,并且将滤波器系数替换为来自第二系数寄存器7的新滤波器,并且它是 使得当第一增益乘法值和第二增益乘法越接近的定时被施加到增益乘法器4的定时被存储在第一系数寄存器2中,当第一增益乘法值的代码与 第二增益乘法值的代码。 IIR型数字滤波器3使用存储在第一系数寄存器2中的滤波器系数进行滤波。 版权所有(C)2008,JPO&INPIT
    • 3. 发明专利
    • Digital filter
    • 数字滤波器
    • JPS59207720A
    • 1984-11-24
    • JP8197483
    • 1983-05-11
    • Toshiba Corp
    • NABESHIMA DAIKI
    • H03H17/00H03H17/02
    • H03H17/0294H03H2017/0295
    • PURPOSE:To enable to give different filter characteristic changing selectively to reproduced audio signals by providing a device that stores plural lines of coefficient data lines and a switching device that leads said coefficient data lines to a cumulative adder. CONSTITUTION:When a switching command signal supplied from a digital demodulation processing circuit 18 has deemphasis instruction, change-over switches S10-S1m of a digital filter 24 are connected respectively to coefficient registers L0-Lm and thereby supplied to coefficient data l0-lm. Filter characteristic at this time has deemphasis characteristic. Accordingly, by cumulative addition of time domain data xn-xn-m line of a digital signal xn to which preemphasis characteristic is added by multipliers a0-am and an adder 243, and coefficient data l0-lm line, high frequency components are removed and deemphasis characteristic is provided and a flat digital signal yn is outputted. By this way, different filter characteristic can be selected automatically and given to preproduced audio signals L', R'.
    • 目的:通过提供存储多条系数数据线的装置和将所述系数数据线引导到累积加法器的开关装置,能够使不同的滤波器特性对再现的音频信号有选择地变化。 构成:当从数字解调处理电路18提供的切换命令信号具有去加重指令时,数字滤波器24的切换开关S10-S1m分别连接到系数寄存器L0-Lm,从而提供给系数数据l0-1m。 此时的滤波特性具有不重要的特点。 因此,通过累积添加由乘法器a0-am和加法器243加上预加重特性的数字信号xn的时域数据xn-xn-m线和系数数据l0-1m线,去除高频分量, 提供去加重特性,并输出平坦的数字信号yn。 通过这种方式,可以自动选择不同的滤波器特性,并给出预先产生的音频信号L',R'。
    • 5. 发明专利
    • Signal processor, television, signal processing method, program and recording medium
    • 信号处理器,电视,信号处理方法,程序和记录介质
    • JP2012039232A
    • 2012-02-23
    • JP2010175389
    • 2010-08-04
    • Sharp Corpシャープ株式会社
    • MURAHASHI YOSHIMITSU
    • H03H17/02G10L21/02G10L21/04H04R3/04
    • H03H17/0461H03H17/0238H03H17/0263H03H17/0286H03H2017/0295H03H2017/0298H03H2017/0477H04R3/00H04R2499/15
    • PROBLEM TO BE SOLVED: To provide a signal processor for making the amount of noise generated in signal processing smaller than before even when it is provided as a signal processor including an inexpensive fixed point operation DSP.SOLUTION: A sound processing section 112 includes: an equalizer section 1121 for making n pieces of biquadratic filters 1121-1 to 1121-n having independent filter characteristics successively act on sound signals; a noise level estimation section 1124 for estimating the size of noise to be outputted from the equalizer section 1121 by making the n pieces of biquadratic filters act in the order to the sound signals for permutation which can be constituted of the n pieces of biquadratic filters; and a filter coefficient setting section 1123 for practically changing the order of making the n pieces of biquadratic filters act on input signals by changing the filter coefficients of the respective biquadratic filters so as to reduce the noise outputted from the equalizer section 1121 on the basis of the estimated size of the noise.
    • 要解决的问题:提供一种信号处理器,用于使信号处理中产生的噪声量比以前更小,即使当其被提供为包括便宜的定点运算DSP的信号处理器时。 解决方案:声音处理部分112包括:均衡器部分1121,用于使n个具有独立滤波器特性的双二次滤波器1121-1至1121-n依次作用在声音信号上; 噪声电平估计部分1124,用于通过使得n个双二次滤波器按照可以由n个双二次滤波器构成的置换声音信号的顺序来估计从均衡器部分1121输出的噪声的大小; 以及滤波器系数设定部分1123,用于通过改变各个二次滤波器的滤波器系数来实际改变使n个双二进制滤波器的顺序对输入信号起作用,以便基于均衡器部分1121输出的噪声 估计的噪音大小。 版权所有(C)2012,JPO&INPIT
    • 9. 发明专利
    • Digital filter
    • 数字滤波器
    • JP2002368583A
    • 2002-12-20
    • JP2001171375
    • 2001-06-06
    • Pioneer Electronic Corpパイオニア株式会社
    • OHASHI TORU
    • H03H17/02H03H17/04
    • H03H17/0294H03H17/04H03H2017/0295
    • PROBLEM TO BE SOLVED: To prevent a noise from being generated when switching a time- constant. SOLUTION: This device is composed of adders 11 and 12, a delay device 13, multipliers 14 and 15, selector 16, multipliers 17 and 18, selector 19, timing generator 20, multipliers 21 and 22 and selector 23. The time constant is switched in two steps by a time-constant control signal St. When the increase of the time-constant is set, coefficients a1 and b1 are selected, and when the decrease of the time-constant is set, coefficient, a2 and b2 are selected. When switching the time-constant from 'large' to 'small', a timing control signal Ssf is outputted by the timing generator 20. When a switching the time-constant from 'small' to 'large', a timing control signal Sfs is outputted. The selector 23 selects a coefficient c1 in respect to the timing control signal Ssf and selects a coefficient c2 respectively just for one clock in respect to the timing control signal Sfs. Thus, the output of the delay 13 is corrected so that noise is not generated at time-constant switching that tends to accompany filter arithmetic operation.
    • 要解决的问题:为了防止在切换时间常数时产生噪声。 解决方案:该装置由加法器11和12,延迟装置13,乘法器14和15,选择器16,乘法器17和18,选择器19,定时发生器20,乘法器21和22以及选择器23组成。时间常数被切换 在时间常数控制信号St.的两步中,当设定时间常数的增加时,选择系数a1和b1,并且当设定时间常数的减小时,选择系数a2和b2。 当将时间常数从“大”切换到“小”时,定时控制信号Ssf由定时发生器20输出。当将时间常数从“小”切换到“大”时,定时控制信号Sfs 输出。 选择器23选择关于定时控制信号Ssf的系数c1,并且相对于定时控制信号Sfs分别选择一个时钟的系数c2。 因此,对延迟13的输出进行校正,使得在伴随滤波器算术运算的时间常数切换时不产生噪声。