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1. 发明专利

JP2018508987A 高密度スプリットゲート型メモリセル审中-公开
公开(公告)号：JP2018508987A
公开(公告)日：2018-03-29
申请号：JP2017539012
申请日：2016-01-19
申请人：シリコンストーリッジテクノロージーインコーポレイテッド , SILICON STORAGE TECHNOLOGY, INC.
发明人：ドーニャン , リウシアン , ティワリヴィピン , トランヒューヴァン
IPC分类号： H01L21/336 , G11C16/04 , H01L27/11521 , H01L29/788 , H01L29/792
CPC分类号： G11C11/419 , G11C16/0458 , G11C16/14 , H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7887
摘要：基板上に、第1の絶縁層、第1の導電層、第2の絶縁層、第2の導電層、第3の絶縁層を形成することを含む、メモリデバイスを形成する方法。第3の絶縁層、第2の導電層、第2の絶縁層、及び第1の導電層を通って第1のトレンチを形成し、第1の導電層の側部を露出させておく。第1の導電層の露出した部分に沿って延伸する第1のトレンチの底部に第4の絶縁層を形成する。第1のトレンチを導電材料で充填する。第3の絶縁層、第2の導電層、第2の絶縁層、及び第1の導電層を通って第2のトレンチを形成する。第2のトレンチの下方に基板内にドレイン領域を形成する。単一の連続チャネル領域が、メモリセル対のドレイン領域間に延伸しているメモリセル対が得られる。

2. 发明专利

JP5350589B2 Transistor having a separate gate structure 有权
公开(公告)号：JP5350589B2
公开(公告)日：2013-11-27
申请号：JP2006532424
申请日：2004-04-16
申请人：フリースケールセミコンダクターインコーポレイテッド
发明人：マシュー、レオ , エフ．シュタイムル、ロバート , ムラリダール、ラマチャンドラン
IPC分类号： H01L29/786 , G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/788 , H01L29/792
CPC分类号： H01L29/785 , G11C16/0458 , G11C16/0475 , H01L27/115 , H01L27/11521 , H01L29/66795 , H01L29/66818 , H01L29/7881 , H01L29/7887 , H01L29/792 , H01L29/7923
摘要： A method of making a transistor with independent gate structures. The gate structures are each adjacent to sidewalls of a semiconductor structure. The method includes depositing at least one conformal layer that includes a layer of gate material over a semiconductor structure that includes the channel region. A planar layer is formed over the wafer. The planar layer has a top surface below the top surface of the rat least one conformal layer at a location over the substrate. The at least one conformal layers are etched to remove the gate material over the semiconductor structure.

3. 发明专利

JP4937444B2 Method of operating a semiconductor device 有权
公开(公告)号：JP4937444B2
公开(公告)日：2012-05-23
申请号：JP2000375551
申请日：2000-12-11
申请人：フリースケールセミコンダクターインコーポレイテッド
发明人：ブルース・イー・ホワイト , ボー・ジャング , ラマチャンドラン・ムラリドハー
IPC分类号： G11C16/02 , H01L29/792 , G11C11/56 , G11C16/04 , G11C16/10 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5628 , G11C11/5671 , G11C16/0458 , G11C16/10 , G11C16/3418 , H01L29/7887
摘要： A method of operating a semiconductor device that includes a first memory cell with discontinuous storage elements or dots (108) in lieu of a conventional floating gate can be programmed to at least one of three different states. The different states are possible because the read current for the memory cell is different when the dots are programmed near the source region or near the drain region. Embodiments may use two different potentials for power supplies or three different potentials. The two-potential embodiment simplifies the design, whereas the three-potential embodiment has a reduced risk of disturb problems in adjacent unselected memory cells (100B, 100C, and 100D).

4. 发明专利

JP2008034497A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008034497A
公开(公告)日：2008-02-14
申请号：JP2006204118
申请日：2006-07-27
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KAWAMURA TETSUSHI , KUME HITOSHI , ARIKANE TAKESHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0416 , G11C16/0425 , G11C16/0433 , G11C16/0458 , G11C16/0491 , G11C16/3427 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/11568
摘要： PROBLEM TO BE SOLVED: To provide a technology of restraining a drain disturbance so as to improve the reliability of a semiconductor device. SOLUTION: For instance, the memory cells of a nonvolatile memory contained in the semicondcutor device each comprises a source (SO) and a drain (DR) which are forned in a p well (PW); a memory node (MN) formed on the p well (PW) between the source (SO) and the drain (DR) through the intermediary of a tunnel insulating film (TNI), and insulated from its surroundings; and a control gate (CG) formed on the memory node (MN) through the intermediary of an interlayer insulating film (ILI). When a writing operation is carried out by channel hot electrons in the above configuration, the p well (PW) is turned electrically floating. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供抑制漏极干扰的技术，以提高半导体器件的可靠性。解决方案：例如，包含在半切割器装置中的非易失性存储器的存储单元各自包括用于p阱（PW）中的源（SO）和漏极（DR）; 通过隧道绝缘膜（TNI）中间形成在源极（SO）和漏极（DR）之间的p阱（PW）上并与其周围绝缘的存储节点（MN）; 以及通过中间层绝缘膜（ILI）介于所述存储节点（MN）上形成的控制栅极（CG）。当在上述结构中通过通道热电子进行写入操作时，p阱（PW）被电浮动。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2007087441A Nonvolatile semiconductor storage apparatus 审中-公开
标题翻译：非易失性半导体存储设备
公开(公告)号：JP2007087441A
公开(公告)日：2007-04-05
申请号：JP2005271769
申请日：2005-09-20
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KATO JUNICHI , SUGIMOTO EI , NAKAYAMA MASAYOSHI , HATTORI NORIO
IPC分类号： G11C16/04 , G11C16/02 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/28 , G11C16/0458 , G11C16/0475 , G11C16/0491
摘要： PROBLEM TO BE SOLVED: To provide a two-transistor current differential detection type nonvolatile semiconductor storage apparatus having excellent area efficiency. SOLUTION: A pair of two transistors is constituted as a cell, sources of the pair of transistors are mutually connected, two transistors of the pair are constituted so as to have respective charge accumulation areas and a group of memory cells 11 each of which can store 2-bit information is arranged like a matrix to constitute a memory cell array 10. A pair of bit lines connected to drains connected on both the outsides of the sources connected in common in the pair of transistors are set as a unit for comparison and a bit line group is connected to a two-input differential detector 13. In reading information, memory cell currents I1, I2 are allowed to flow into a pair of transistors in the memory cell simultaneously in a mutually independent state, respective current amounts are compared with each other by the differential detector 13 through a pair of bit lines which is a unit of comparison and the information is read out by the difference. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供具有优异的面积效率的双晶体管电流差动检测型非易失性半导体存储装置。解决方案：一对两个晶体管被构成为单元，该对晶体管的源极相互连接，该对中的两个晶体管构成为具有各自的电荷累积区域和一组存储单元11 可以存储2位信息的阵列被布置成矩阵以构成存储单元阵列10.连接到在一对晶体管中共同连接的源极的外部连接的漏极的一对位线被设置为比较和位线组连接到双输入差分检测器13.在读取信息中，允许存储器单元电流I1，I2以相互独立的状态同时流入存储器单元中的一对晶体管，各自的电流量通过作为比较单位的一对位线由差分检测器13进行比较，并且通过该差读出信息。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2006128703A Semiconductor device including multi-bit non-volatile memory cell and manufacture method therefor 有权
标题翻译：包含多位非易失性存储器单元的半导体器件及其制造方法
公开(公告)号：JP2006128703A
公开(公告)日：2006-05-18
申请号：JP2005315324
申请日：2005-10-28
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： SEO BO-YOUNG , JEON HEE-SEOG , KANG SUNG-TAEG
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5692 , G11C16/0458 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that includes a multi-bit non-volatile memory cell and its manufacture method.
SOLUTION: The non-volatile semiconductor device includes a unit cell, comprising a plurality of transistors the source and drain regions of which are shared, wherein each of the plurality of transistors includes at least one control gate and at least one charge accumulation region, and each control gate is connected to at least one control voltage for shifting the threshold voltage of each transistor. Due to this, it is possible to effectively increase the degree of integration and efficiently reduce the cost per megabyte of a flash EEPROM.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种包括多位非易失性存储单元的半导体器件及其制造方法。解决方案：非易失性半导体器件包括单元，其包括多个晶体管，源极和漏极区域共享，其中每个晶体管包括至少一个控制栅极和至少一个电荷积累区域，并且每个控制栅极连接至至少一个控制电压以移位每个晶体管的阈值电压。由此，可以有效地提高集成度并有效降低闪存EEPROM的每兆字节的成本。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2005353646A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2005353646A
公开(公告)日：2005-12-22
申请号：JP2004169660
申请日：2004-06-08
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： HARAGUCHI KEIICHI , KATO MASATAKA , KANEMITSU KENJI
IPC分类号： H01L21/8247 , G11C11/34 , G11C16/04 , H01L27/10 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G11C16/0458 , H01L27/11521 , H01L29/42328 , H01L29/7887
摘要： PROBLEM TO BE SOLVED: To promote microfabrication and large capacitance of a nonvolatile semiconductor memory device.
SOLUTION: The memory cell MC of a flash memory is formed of a field-effect type transistor which is provided with: a first gate insulating film 5 formed on the surface of a p-type well 3; a selection gate 7 which is formed on the first gate insulating film 5 and whose side surfaces and upper surface are covered with a silicon oxide film (first insulating film) 6; a floating gate 8 which is formed like a side wall on both sides of the selection gate 7 and is electrically isolated from the selection gate 7 by means of the silicon oxide film 6; a second gate insulating film 9 that is formed so as to cover the respective surfaces of the silicon oxide film 6 and the floating gate 8; and a control gate 10 formed on the upper side of the second insulating film 9.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：促进非易失性半导体存储器件的微细加工和大电容。解决方案：闪速存储器的存储单元MC由场效应晶体管形成，该场效应晶体管设置有：形成在p型阱3的表面上的第一栅极绝缘膜5; 选择栅极7，其形成在第一栅极绝缘膜5上，并且其侧表面和上表面被氧化硅膜（第一绝缘膜）6覆盖; 浮栅8，其在选择栅极7的两侧形成为侧壁，并通过氧化硅膜6与选择栅极7电隔离; 形成为覆盖氧化硅膜6和浮动栅极8的各个表面的第二栅极绝缘膜9; 以及形成在第二绝缘膜9的上侧的控制栅极10.版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2005537597A Column decoding and pre-charging of the flash memory device 审中-公开
公开(公告)号：JP2005537597A
公开(公告)日：2005-12-08
申请号：JP2004530795
申请日：2003-06-10
申请人：スパンションエルエルシー
发明人：ウォング，キース , クリハラ，カズヒロ , シエー，ミング−フエイ , チェン，ポー−リング , エスチュング，マイケル , ヤング，ティエン−チュン
IPC分类号： G11C16/06 , G11C16/04 , G11C16/26
CPC分类号： G11C16/26 , G11C16/0458 , G11C16/0475 , G11C16/0491
摘要：メモリセルを読み出す方法及びこの方法を使用するメモリアレイが記載されている。メモリセルのグループは、行（次元Ｘ）及び列（次元Ｙ）を有する矩形状アレイに配置される。１行の範囲内で、メモリセルのソース及びドレインが接続され、直線状チェインを形成する。共通ワードラインは行内の各ゲートに接続される。別個の列ラインがチェインの隣接したメモリセルの間の各ノードに接続される。４列Ｙ方向デコーダが検知動作のための列ラインを選択するため使用される。電圧源はこの検知動作中に４本の列ラインのうちの２本に供給される。プリチャージングのため、電気負荷がメモリアレイの第１のノードに印加される。メモリアレイの同じワードライン内の少なくとも一つの中間ノードによって第１のノードから隔てられた第２のノードはプリチャージされる。

9. 发明专利

JP2005063516A Write-in method of nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件的写入方法
公开(公告)号：JP2005063516A
公开(公告)日：2005-03-10
申请号：JP2003289838
申请日：2003-08-08
申请人： Sharp Corp , シャープ株式会社
发明人： ONO TAKASHI , WATANABE MASAHIKO
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/06
CPC分类号： G11C16/0458 , G11C11/5628
摘要： PROBLEM TO BE SOLVED: To provide a write-in method, by which multi-level data can be written at high speed, in a nonvolatile semiconductor memory device, in which a memory cell can store data of ternary level or higher. SOLUTION: When at least one threshold voltage range corresponding to the other storage state exists between a threshold voltage range, corresponding to a storage state before write-in and a threshold voltage range corresponding to a storage state, after write-in in a write-in object memory cell, after at least one first write-in gate voltage corresponding respectively to at least one other storage state, a first write-in process to which the prescribed write-in drain voltage is applied; a second write-in gate voltage corresponding to a write-in state after write-in, and a second write-in process to which the prescribed write-in drain voltage is applied are performed respectively for the write-in object memory cells; and a verify process by which it is verified whether write-in is performed for the write-in object memory cell is performed. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种在非易失性半导体存储器件中提供多级数据可以被高速写入的写入方法，其中存储器单元可以存储三元级或更高级的数据。解决方案：当在写入之后对应于对应于存储状态的存储状态的阈值电压范围和与存储状态相对应的阈值电压范围之间存在对应于另一个存储状态的至少一个阈值电压范围时，写入对象存储单元，在分别对应于至少一个其他存储状态的至少一个第一写入栅极电压之后，施加规定的写入漏极电压的第一写入过程; 对写入对象存储单元分别执行对应于写入后的写入状态的第二写入栅极电压和施加规定的写入漏极电压的第二写入处理; 以及执行验证是否对写入对象存储单元执行写入是否被执行。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2004349341A Semiconductor storage element, semiconductor device, their manufacturing methods, portable electronic equipment, and ic card 审中-公开
公开(公告)号：JP2004349341A
公开(公告)日：2004-12-09
申请号：JP2003142277
申请日：2003-05-20
申请人： Sharp Corp , シャープ株式会社
发明人： OGURA TAKAYUKI , IWATA HIROSHI , SHIBATA AKIHIDE
IPC分类号： H01L21/8234 , G11C16/04 , H01L21/28 , H01L21/8247 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： B82Y10/00 , G11C16/0458 , G11C2216/06 , H01L21/28273 , H01L29/42332 , H01L29/7887
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage element that is hardly lowered in memory characteristics.
SOLUTION: The semiconductor storage element is provided with memory function groups 11 on both sides of a gate electrode 3 formed on a semiconductor substrate 1 through a gate insulating film 2. The memory function groups 11 are composed of charge holders constituted by forming inclusive insulating films 21 having nearly uniform thicknesses on the surfaces of silicon dots 10 having charge accumulating functions, and side-wall insulators 16 covering the charge holding sections. The semiconductor storage element is also provided with offset regions 20 formed by offsetting the ends of source/drain regions 13 with respect to the ends of the gate electrode 3 in the longitudinal direction of a gate. The storing states of the memory function groups 11 are detected by detecting the current quantity between the two source/drain regions 13 which changes depending upon the quantity of charges held in the charge holding sections. The fall of the memory characteristics of the semiconductor storage element is prevented by preventing the dissipation of the charges accumulated in the silicon dots 10 by means of the inclusive insulating films 21.
COPYRIGHT: (C)2005,JPO&NCIPI

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