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    • 4. 发明专利
    • DATA TERMINAL DEVICE
    • JPS58119073A
    • 1983-07-15
    • JP75482
    • 1982-01-06
    • SHINKO ELECTRIC CO LTD
    • OKAZAKI KENJI
    • G07C1/00
    • PURPOSE:To drive away a feeling of uneasiness for an input omission from operator by providing facilities for confirming at least either of up-to-date information inputted to a terminal device and up-to-date input time. CONSTITUTION:A card is inserted into a data terminal device 1 to read data on the card through a card reader 2a and after the operation of an operation part 3, a CPU7 transmits the data to an electronic computer 8 through a transmission line 9 and also stores the read data and transmission time in a storage device 6. The electronic computer 8 stores the sent data and reception time. Then when an operator operates a confirmation collation switch 5, data is read out of the storage part 6 and displayed on a display part 4. Consequently, the operator confirms the input to eliminate the feeling of uneasiness for an input omission. This suits to a time card terminal device.
    • 6. 发明专利
    • Circuit for detecting computer runaway
    • 检测计算机RUNAWAY的电路
    • JPS61109151A
    • 1986-05-27
    • JP22964784
    • 1984-10-31
    • Shinko Electric Co Ltd
    • OKAZAKI KENJI
    • G06F11/00G06F11/07
    • G06F11/073G06F11/0703
    • PURPOSE:To obtain various indication data for processing actions when a computer has a runaway by setting a detection area in response to a non-using area, etc. of a memory space. CONSTITUTION:Address input terminals a0-a9 of a ROM1 are connected to an address bus of a CPU. The output signal of a mode selection switch 3 is supplied to address input terminals a10-a13 respectively of the ROM1. The ROM1 outputs properly an output signal in response to the address received an access. This output signal is decoded by a decoder 7 and supplied to a memory circuit 8. The circuit 8 stores the output signals of both the decoder 7 and a timer 9 and outputs a control signal and an instruction code to the CPU based on the result of storage of the circuit 8.
    • 目的:通过响应于存储空间的不使用区域等设置检测区域来获得计算机失控时的处理动作的各种指示数据。 构成:将ROM1的地址输入端子a0-a9连接到CPU的地址总线。 模式选择开关3的输出信号分别提供给ROM1的地址输入端子a10-a13。 响应于接收到的地址,ROM1正确地输出输出信号。 该输出信号由解码器7解码并提供给存储电路8.电路8存储解码器7和定时器9的输出信号,并根据以下结果输出控制信号和指令码给CPU 存储电路8。
    • 7. 发明专利
    • System for automatically designing printed board pattern
    • 自动设计印刷板图案的系统
    • JPS59109971A
    • 1984-06-25
    • JP22104482
    • 1982-12-15
    • Shinko Electric Co Ltd
    • OKAZAKI KENJI
    • G03F1/00G06F17/50H05K3/00
    • G06F17/509G06F17/5068H05K3/0005
    • PURPOSE:To set a rand inhibted area for a fixed area around the center of a through hole based on the coordinate, by discriminating the coordinates of positions in the inhibited area, and, when the next indicated coordinate is in the inhibited area, to make the indication invalid. CONSTITUTION:At the time of installing through holes 4 (A-c) to a printed board 1 from the surface to the back, a designer indicates the position of the through holes 4 with a write pen. A rand inhibited area D is installed for a fixed area around the center of the through holes 4 based on the coordinate and whether an indicated coordinate is in the inhibited area D or not is discriminated by a discriminating circuit. When a coordinate indicated by a designer with the write pen is in the inhibited area D, the indication is made invalid and erased, so that the operation of a printed board automatically designing system becomes easier.
    • 目的:通过基于坐标对通孔中心周围的固定区域设置兰特抑制区域,通过区分禁止区域中的位置坐标,并且当下一个指示坐标处于禁止区域时,使 指示无效。 构成:在从表面到背面安装通孔4(A-c)到印刷电路板1时,设计者用写笔指示通孔4的位置。 基于坐标,基于坐标来确定通孔4的中心周围的固定区域的兰特抑制区域D,以及通过识别电路来判别指示的坐标是否在禁止区域D中。 当由设计者用写笔指示的坐标处于禁止区域D时,指示被无效并被擦除,使得印刷板自动设计系统的操作变得更容易。
    • 8. 发明专利
    • MEMORY CIRCUIT
    • JPS6050688A
    • 1985-03-20
    • JP15768983
    • 1983-08-29
    • SHINKO ELECTRIC CO LTD
    • OKAZAKI KENJI
    • G06F12/06G11C8/00
    • PURPOSE:To ensure coping with a same circuit configuration despite the change of a memory map by setting a memory map after decoding a specific bit of an address signal via an ROM with the written memory map. CONSTITUTION:An access is given to an ROM4 where a memory map is written and set by the selection provided by a map mode selection switch 7 and specific bits A0, A14, A15, etc. of addresses A0-A15, etc. given from a CPU via a bus driver 1. Then map setting information S1-S3 are delivered together with write and read control commands R and W via a decoding circuit 8. The bus drivers 5 and 6 corresponding to an RAM2 and an ROM3 formed on the same substrate respectively are activated in response to the information S1-S3 to set a memory map. Thus it is possible to ensure the same coping with the same circuit configuration with no change of a pattern despite the change of the memory map. This improves the productivity of memory circuits.