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    • 1. 发明专利
    • Integrated circuit for musical sound generation device
    • 用于音乐发声装置的集成电路
    • JP2009244751A
    • 2009-10-22
    • JP2008093479
    • 2008-03-31
    • Yamaha Corpヤマハ株式会社
    • KAWAMOTO RYUICHIKATO HISAOOKAMURA KAZUHISA
    • G10H1/00
    • PROBLEM TO BE SOLVED: To prevent degradation in operation performance of a CPU and a sound source section, in an integrated circuit connected with an external ROM in which a program and data for a sound source are stored. SOLUTION: A program and a waveform ROM 3 are externally connected to a sound source LSI 1 via an external memory input and output section comprising selector 12, a gate circuit 13 and an S signal generation circuit 14. When an electronic musical instrument 1 starts operation, the S signal generation section 14 outputs a first selection information, and the first selection information is set in the selector 12, and the CPU 10 can access to the external ROM 3. The CPU 10 transfers a program body from the external ROM 3 to a RAM, and jumps to a transfer destination. The CPU 10 executes the program from the RAM of a jump destination, and second selection information is output from the S signal generation section 14, and it is set in the selector 12. After that, the sound source section 11 can access to the external ROM 3. The CPU 10 executes the program from the RAM and controls operation of an electronic musical instrument 2. COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:为了防止与存储有程序和声源的数据的外部ROM连接的集成电路中的CPU和声源部的操作性能的劣化。 解决方案:程序和波形ROM3经由包括选择器12,门电路13和S信号发生电路14的外部存储器输入和输出部分外部连接到声源LSI 1.当电子乐器 1开始操作时,S信号产生部分14输出第一选择信息,并且第一选择信息被设置在选择器12中,并且CPU 10可以访问外部ROM 3.CPU 10从外部传送节目主体 ROM 3到RAM,并跳转到传送目的地。 CPU10从跳转目的地的RAM执行程序,并且从S信号产生部分14输出第二选择信息,并将其设置在选择器12中。此后,声源部分11可以访问外部 ROM3。CPU10从RAM执行程序并控制电子乐器2的操作。版权所有:(C)2010,JPO&INPIT
    • 2. 发明专利
    • Sound source device
    • JP2004109686A
    • 2004-04-08
    • JP2002273966
    • 2002-09-19
    • Yamaha Corpヤマハ株式会社
    • OKAMURA KAZUHISA
    • G10H7/00G10H7/02G10H7/08
    • PROBLEM TO BE SOLVED: To improve the efficiency of access to a storage means by properly arbitrating requests to access the storage means through simple processing. SOLUTION: A sound source device is provided with a sound source part 32 which generates a speech signal on the basis of speech data and a CPU 1 which controls the operation of the device, and allows both the sound source part 32 and CPU 11 to access the same memory. Further, the device is provided with an external memory 4 with a slow access speed, and an internal SRAM 19 and an internal ROM 18 with faster access speeds. When an access request from the sound source part 32 to the external memory 4 and an access request from the CPU 11 to the external memory 4 compete each other, an external bus arbitration part 15 performs arbitration giving priority to the access request from the sound source part 32, and when access requests to the internal SRAM 19 and internal ROM 18 compete, arbitration parts 16 and 17 performs arbitration allowing access of a higher frequency from the CPU 11 than access from the sound source part 32. COPYRIGHT: (C)2004,JPO
    • 4. 发明专利
    • Semiconductor integrated circuit and acoustic signal processing unit
    • 半导体集成电路和声音信号处理单元
    • JP2007258780A
    • 2007-10-04
    • JP2006076685
    • 2006-03-20
    • Yamaha Corpヤマハ株式会社
    • OKAMURA KAZUHISATAKEISHI EIICHI
    • H04R3/00
    • PROBLEM TO BE SOLVED: To reduce the load of a CPU required for scanning the state of a button.
      SOLUTION: In an integrated circuit 10 having the CPU 11 and the button RAM 35 that can be accessed from the CPU 11, there are provided a scan control section 31 that accesses a button circuit 48 having a plurality of buttons except the CPU 11 for outputting an analog signal for indicating the state of each button periodically and successively; an ADC 32 for converting a signal outputted by the button circuit 48 to digital data; a change width restriction circuit; and an LPF 34. The converted digital data are written to the button RAM 35.
      COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题:减少扫描按钮状态所需的CPU的负载。 解决方案:在具有可从CPU 11访问的CPU 11和按钮RAM35的集成电路10中,设置有扫描控制部分31,其访问具有除了CPU之外的多个按钮的按钮电路48 11,用于周期性和连续地输出用于指示每个按钮的状态的模拟信号; 用于将由按钮电路48输出的信号转换为数字数据的ADC 32; 变宽限制电路; 和LPF 34.转换后的数字数据被写入按钮RAM 35.版权所有(C)2008,JPO&INPIT
    • 5. 发明专利
    • Musical tone generator
    • 音乐发音器
    • JP2005165355A
    • 2005-06-23
    • JP2005020986
    • 2005-01-28
    • Yamaha Corpヤマハ株式会社
    • OKAMURA KAZUHISAICHIKI TETSUJI
    • G10H1/00
    • PROBLEM TO BE SOLVED: To reduce the electric power consumption of an electronic musical instrument for pipeline processing of musical tone signals. SOLUTION: A read-out circuit 202, a DSP 205, etc., synthesize/process the musical tone signals of a plurality of channels by each of sampling periods in synchronization with a clock signal ψ. A sound production channel block control section 231 and a DSP clock control section 232 output mask signals Sa to Sd which mask the clock signal ψ only in the period not actually used in the respective sampling periods. As a result, the operations of the read-out circuit 202 and the DSP 205 stop and therefore the electric power consumption is reduced. COPYRIGHT: (C)2005,JPO&NCIPI
    • 要解决的问题:降低用于音乐信号的流水线处理的电子乐器的电力消耗。 解决方案:与时钟信号ψ同步,每个采样周期,读出电路202,DSP205等合成/处理多个通道的乐音信号。 声音产生通道块控制部分231和DSP时钟控制部分232输出仅在各个采样周期内实际不使用的时段内屏蔽时钟信号ψ的屏蔽信号Sa至Sd。 结果,读出电路202和DSP 205的操作停止,因此降低了电力消耗。 版权所有(C)2005,JPO&NCIPI
    • 6. 发明专利
    • Sound generator
    • 声音发生器
    • JP2014092723A
    • 2014-05-19
    • JP2012244003
    • 2012-11-05
    • Yamaha Corpヤマハ株式会社
    • TSUCHIYA HIROYUKIOKAMURA KAZUHISATAKEISHI EIICHIADACHI TAKAHIRO
    • G10H7/02G06F12/02G10H1/00
    • PROBLEM TO BE SOLVED: To provide a sound generator capable of reading data at a high speed from a memory for storing waveform sample data and a program read by a CPU in a waveform memory sound source is accelerated to attain increase in the number of simultaneous sound generation and higher-speed operation of the CPU.SOLUTION: A memory for storing waveform data includes a memory capable of: receiving an instruction code and an address in a first reading to output data of the address; omitting an instruction code and receiving only an address to output data in a second and subsequent reading; and setting a continuous reading mode. An access part reads waveform samples from the start address to supply to a sound source part by setting the memory to the continuous reading mode in the first reading at the time of power-up and performing access by only an address omitting an instruction code according to a waveform sample requirement for each channel from the sound source part.
    • 要解决的问题:为了提供能够从用于存储波形采样数据的存储器高速读取数据的声音发生器,并且由CPU在波形存储器声源中读取的程序被加速以实现同时声音数量的增加 存储波形数据的存储器包括能够:在一读中接收指令代码和地址以输出地址的数据的存储器; 省略指令码并仅接收地址以在第二次和随后的读取中输出数据; 并设置连续读取模式。 访问部分从起始地址读取波形样本以通过在上电时将存储器设置为连续读取模式,而仅通过省略根据以下内容的指令代码的地址进行存取: 来自声源部分的每个声道的波形采样要求。
    • 7. 发明专利
    • Waveform data processing apparatus
    • 波形数据处理设备
    • JP2004102136A
    • 2004-04-02
    • JP2002266878
    • 2002-09-12
    • Yamaha Corpヤマハ株式会社
    • OKAMURA KAZUHISA
    • G10H1/00G10H7/02H04L12/28
    • PROBLEM TO BE SOLVED: To increase the versatility of a sound source board, such as a sound source board mounted on an electronic musical instrument, by freely setting the logical connection state of a plurality of LSIs. SOLUTION: An LSI (e.g. a sound source, an effector, etc.) constitutes a "node" connected to a common bus. To each node, one or more transmission frames are allocated in one sampling period. In an allocated transmission frame, the node serves as a transmission node to output a clock signal ACLK and also to output a data signal ADAT asynchronously with it. Nodes other than the transmission node operate as reception nodes upon occasion to receive the signals. At each node, the rise frequency of a frame signal AFRM is counted and then the frame number is detected. COPYRIGHT: (C)2004,JPO
    • 要解决的问题:通过自由设定多个LSI的逻辑连接状态,来增加安装在电子乐器上的声源板等声源板的通用性。 解决方案:LSI(例如声源,效应器等)构成连接到公共总线的“节点”。 对于每个节点,在一个采样周期中分配一个或多个传输帧。 在分配的传输帧中,节点用作传输节点以输出时钟信号ACLK,并且与其异步地输出数据信号ADAT。 发送节点以外的节点在接收信号的情况下作为接收节点工作。 在每个节点处,对帧信号AFRM的上升频率进行计数,然后检测帧号。 版权所有(C)2004,JPO
    • 8. 发明专利
    • Acoustic signal processor
    • 声音信号处理器
    • JP2010039265A
    • 2010-02-18
    • JP2008202925
    • 2008-08-06
    • Yamaha Corpヤマハ株式会社
    • OKAMURA KAZUHISA
    • G10H1/00
    • PROBLEM TO BE SOLVED: To prevent a noise from being generated and quality from being deteriorated in a waveform data, when generating synchronized word clock with a plurality of serially connected LSIs. SOLUTION: A master LSI 10 and a slave LSI 120 generate operation clocks synchronized with the same synchronization clock, the operation clocks are counted by operation counters 15, 25, to generate respectively the first word clock and the second word clock. An RT correction part 27 of the slave LSI 120 determines whether a count value of the operation counter 25 at a time point in timing inputted with the first word clock from the master LSI 10 comes within a prescribed range corresponding to an allowance limit of phase shift of a transmission clock in serial communication or not, the operation counter 25 is reset when not coming within the prescribed range, and count timing of the operation counter 25 is made to conform to count timing of the operation counter 15. COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:为了防止在波形数据中产生噪声和质量劣化,当产生具有多个串联LSI的同步字时钟时。 主LSI10和从LSI120产生与同步同步时钟同步的工作时钟,操作时钟由操作计数器15,25计数,分别产生第一字时钟和第二字时钟。 从LSI 120的RT校正部27确定在从主LSI 10输入的第一字时钟输入的定时时刻的运算计数器25的计数值是否在与相移允许极限对应的规定范围内 的串行通信中的传输时钟,当不在规定的范围内时,操作计数器25被复位,并且使得操作计数器25的计数定时与操作计数器15的计数定时一致。

      版权: (C)2010,JPO&INPIT

    • 9. 发明专利
    • Musical sound generating device
    • 音乐声音发生器
    • JP2008089642A
    • 2008-04-17
    • JP2006267167
    • 2006-09-29
    • Yamaha Corpヤマハ株式会社
    • ITO KAZUYUKIKAWAMOTO RYUICHISHIRAHAMA TAROOKAMURA KAZUHISA
    • G10H7/02
    • PROBLEM TO BE SOLVED: To provide a musical sound generating device which starts generating a new sound without delay. SOLUTION: A register 14 of a sound source means 1 comprises a first buffer group 15 stored with parameters as objects of synchronous writing and a second buffer group 16 stored with parameters other than the objects of synchronous writing. A busy flag is set on during a period of writing of the parameters as the objects of synchronous writing to the first buffer group 15, but it is made possible to access the second buffer group 16 and write/read the parameters other than the objects of synchronous writing. COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题:提供一种立即开始产生新声音的音乐声音产生装置。 解决方案:声源装置1的寄存器14包括存储有作为同步写入对象的参数的第一缓冲器组15和存储有除了同步写入对象之外的参数的第二缓冲器组16。 在作为对第一缓冲器组15的同步写入的对象的参数写入期间设置忙标志,但是可以访问第二缓冲器组16并且读取除了对象之外的参数 同步写作。 版权所有(C)2008,JPO&INPIT
    • 10. 发明专利
    • Signal processor
    • 信号处理器
    • JP2005215683A
    • 2005-08-11
    • JP2005020985
    • 2005-01-28
    • Yamaha Corpヤマハ株式会社
    • OKAMURA KAZUHISAICHIKI TETSUJI
    • G06F1/32G06F1/04G06F9/445G10H1/00
    • PROBLEM TO BE SOLVED: To reduce power consumption of an electronic musical instrument which carries out pipeline processings of a musical sound signal. SOLUTION: A readout circuit 202, a DSP 205, etc., carries out synthesis and processing of musical sound signals of a plurality of channels for each sampling cycle, in synchronism with clock signal ϕ. A sounding channel clock control part 231 and a DSP clock control part 232 output mask signals Sa to Sd masking the clock signal ϕ only for the period which is not actually being used in each sampling cycle. Consequently, the read circuit 202 and DSP 205 stops operating, so that power consumption is reduced. COPYRIGHT: (C)2005,JPO&NCIPI
    • 要解决的问题:为了减少对音乐声音信号进行流水线处理的电子乐器的功耗。 解决方案:与时钟信号φ同步,读出电路202,DSP205等针对每个采样周期执行多个通道的音乐声音信号的合成和处理。 探测通道时钟控制部分231和DSP时钟控制部分232输出屏蔽信号Sa至Sd仅在每个采样周期内实际不使用的时段屏蔽时钟信号φ。 因此,读取电路202和DSP 205停止工作,从而降低功耗。 版权所有(C)2005,JPO&NCIPI