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1. 发明专利

JP2005215683A Signal processor 有权
标题翻译：信号处理器
公开(公告)号：JP2005215683A
公开(公告)日：2005-08-11
申请号：JP2005020985
申请日：2005-01-28
申请人： Yamaha Corp , ヤマハ株式会社
发明人： OKAMURA KAZUHISA , ICHIKI TETSUJI
IPC分类号： G06F1/32 , G06F1/04 , G06F9/445 , G10H1/00
摘要： PROBLEM TO BE SOLVED: To reduce power consumption of an electronic musical instrument which carries out pipeline processings of a musical sound signal. SOLUTION: A readout circuit 202, a DSP 205, etc., carries out synthesis and processing of musical sound signals of a plurality of channels for each sampling cycle, in synchronism with clock signal ϕ. A sounding channel clock control part 231 and a DSP clock control part 232 output mask signals Sa to Sd masking the clock signal ϕ only for the period which is not actually being used in each sampling cycle. Consequently, the read circuit 202 and DSP 205 stops operating, so that power consumption is reduced. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了减少对音乐声音信号进行流水线处理的电子乐器的功耗。解决方案：与时钟信号φ同步，读出电路202，DSP205等针对每个采样周期执行多个通道的音乐声音信号的合成和处理。探测通道时钟控制部分231和DSP时钟控制部分232输出屏蔽信号Sa至Sd仅在每个采样周期内实际不使用的时段屏蔽时钟信号φ。因此，读取电路202和DSP 205停止工作，从而降低功耗。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2005165355A Musical tone generator 有权
标题翻译：音乐发音器
公开(公告)号：JP2005165355A
公开(公告)日：2005-06-23
申请号：JP2005020986
申请日：2005-01-28
申请人： Yamaha Corp , ヤマハ株式会社
发明人： OKAMURA KAZUHISA , ICHIKI TETSUJI
IPC分类号： G10H1/00
摘要： PROBLEM TO BE SOLVED: To reduce the electric power consumption of an electronic musical instrument for pipeline processing of musical tone signals. SOLUTION: A read-out circuit 202, a DSP 205, etc., synthesize/process the musical tone signals of a plurality of channels by each of sampling periods in synchronization with a clock signal ψ. A sound production channel block control section 231 and a DSP clock control section 232 output mask signals Sa to Sd which mask the clock signal ψ only in the period not actually used in the respective sampling periods. As a result, the operations of the read-out circuit 202 and the DSP 205 stop and therefore the electric power consumption is reduced. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：降低用于音乐信号的流水线处理的电子乐器的电力消耗。解决方案：与时钟信号ψ同步，每个采样周期，读出电路202，DSP205等合成/处理多个通道的乐音信号。声音产生通道块控制部分231和DSP时钟控制部分232输出仅在各个采样周期内实际不使用的时段内屏蔽时钟信号ψ的屏蔽信号Sa至Sd。结果，读出电路202和DSP 205的操作停止，因此降低了电力消耗。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2003271150A Multitrack player, multitrack recorder and multitrack recorder/player 有权
标题翻译：多媒体播放器，多媒体记录器和多媒体记录器/播放器
公开(公告)号：JP2003271150A
公开(公告)日：2003-09-25
申请号：JP2002077045
申请日：2002-03-19
申请人： Yamaha Corp , ヤマハ株式会社
发明人： ICHIKI TETSUJI , SHIMIZU MASAHIRO
IPC分类号： G10H7/02
摘要： PROBLEM TO BE SOLVED: To prevent a high interrupt repititions to a controlling means so as not to be fluctuative. SOLUTION: Buffer memories used in recording and playing a multitrack are formed on a waveform memory. The size of each of the buffer memories is determined by the sampling frequency of stream waveform data to be stored and the number of bits per sample. In each buffer memory to be a double buffer configuration, the timing of writing/reading end in performing writing/reading corresponding to a sampling period consequently coincides with one another. Then, it is possible to eliminate the need to respectively transmit an interrupt request for data transfer in a plurality of buffer memories. The transmission timing of the interrupt request becomes a prescribed period. COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：防止对控制装置的高中断重复，以免变动。解决方案：在波形存储器中形成用于记录和播放多轨的缓冲存储器。每个缓冲存储器的大小由待存储的流波形数据的采样频率和每个样本的位数确定。在每个缓冲存储器中，作为双缓冲器配置，在与采样周期相对应的写入/读取期间写入/读取结束的定时因而彼此一致。然后，可以消除在多个缓冲存储器中分别发送数据传输的中断请求的需要。中断请求的发送定时成为规定期间。版权所有（C）2003，JPO

4. 发明专利

JP2005210190A Sampling frequency conversion apparatus 有权
标题翻译：采样频率转换装置
公开(公告)号：JP2005210190A
公开(公告)日：2005-08-04
申请号：JP2004011906
申请日：2004-01-20
申请人： Yamaha Corp , ヤマハ株式会社
发明人： ICHIKI TETSUJI , KAWAI SHIZUHIKO
IPC分类号： H03H17/00 , H03H17/06
摘要： PROBLEM TO BE SOLVED: To perform frequency conversion with a small buffer size for arbitrary input/output sampling frequencies Fin, Fout.
SOLUTION: A counter 204 counts input CKin, and supplies a writing address wad of input data Din to FIFO 206. A full adder 218 accumulates a signal Delta (substantially Fin/Fover) for every over-sampling clock CKover, and generates a signal SH every time a result of accumulation exceeds "1". A counter 202 reads the result of counting of the signal SH, and outputs the result as a reading address rad. A full adder 212 or the like minutely adjusts the value of Delta on the basis of "wad-rad". In this case, if the Fin or Fover varies rapidly, the value of Delta is forcibly set on the basis of an actual measurement value of the Fin/Fout via a selector 215. Then, the sensitivity of a minute adjustment value for "wad-rad" is increased and convergence of the Delat is promoted.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了对任意输入/输出采样频率Fin，Fout执行小缓冲大小的频率转换。解决方案：计数器204对输入CKin进行计数，并将输入数据Din的写入地址串提供给FIFO 206.全加器218对每个过采样时钟CKover累加信号Delta（基本上为Fin / Fover），并产生每次累积结果超过“1”的信号SH。计数器202读取信号SH的计数结果，并输出结果作为读取地址rad。全加器212等基于“wad-rad”精确地调整Delta的值。在这种情况下，如果Fin或Fover变化很快，则通过选择器215根据Fin / Fout的实际测量值强制设定Delta的值。然后，对于“wad- rad“增加，Delat的融合得到提升。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2004227004A Memory using sound source device 有权
公开(公告)号：JP2004227004A
公开(公告)日：2004-08-12
申请号：JP2004083463
申请日：2004-03-22
申请人： Yamaha Corp , ヤマハ株式会社
发明人： ICHIKI TETSUJI
IPC分类号： G10H7/00
摘要： PROBLEM TO BE SOLVED: To contrive a way of sending and receiving data to and from a processor. SOLUTION: A musical sound generating means includes an address counter means which operates for time-division channel processing and in which an address for musical sound generation is set as indicated by the processor, and reads data for a sound source out of a memory according to the set address. A control means sets an address for data writing in the address counter means and the data to be written are written to a buffer when the data are written from the processor to the memory. The musical sound generating means writes the data in the buffer to the memory according to the address for data writing set in the address counter means by using a free channel among time-division channels. Similarly, when the processor reads the data out of the memory, the data read out by using a free channel are saved in the buffer. COPYRIGHT: (C)2004,JPO&NCIPI

6. 发明专利

JP2005215699A Sound source device 有权
标题翻译：声源设备
公开(公告)号：JP2005215699A
公开(公告)日：2005-08-11
申请号：JP2005085577
申请日：2005-03-24
申请人： Yamaha Corp , ヤマハ株式会社
发明人： ICHIKI TETSUJI
IPC分类号： G10H7/00
摘要： PROBLEM TO BE SOLVED: To obtain a CODEC function without having to additionally install buffers. SOLUTION: A region 41a, obtained by dividing an FIFO, is used as a CPU access buffer, when a CPU reads and writes waveform data directly out of and to a waveform memory. Regions 41b and 41c, obtained by dividing the FIFO, are used as output CODEC buffer and input CODEC buffer for handling audio data inputted to a sound source section by the CPU. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：获得CODEC功能而无需额外安装缓冲区。解决方案：当CPU将波形数据直接读出并写入波形存储器时，通过划分FIFO获得的区域41a用作CPU存取缓冲器。将通过划分FIFO获得的区域41b和41c用作用于处理由CPU输入到声源部分的音频数据的输出CODEC缓冲器和输入CODEC缓冲器。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2005208682A Waveform memory type musical sound synthesizing device 有权
标题翻译：波形记忆类型音乐合成装置
公开(公告)号：JP2005208682A
公开(公告)日：2005-08-04
申请号：JP2005113397
申请日：2005-04-11
申请人： Yamaha Corp , ヤマハ株式会社
发明人： ICHIKI TETSUJI
IPC分类号： G10H7/02
摘要： PROBLEM TO BE SOLVED: To provide a waveform memory type musical sound synthesizing device that flexibly sets constitution of a waveform memory to and sufficiently derives performance of various waveform memories. SOLUTION: Based upon an address signal for accessing a memory device, kinds (memory type signals TYPEH and TYPEL) of the memory device are generated. Timing generating circuits 346 and 362 control timing of an output enable signal, a write enable signal, the address signal, etc., based upon those memory type signals. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种波形存储器型音乐合成装置，其灵活地设置波形存储器的构成并充分地导出各种波形存储器的性能。解决方案：基于用于访问存储器件的地址信号，生成存储器件的种类（存储器类型信号TYPEH和TYPEL）。定时产生电路346和362基于这些存储器类型信号来控制输出使能信号的定时，写使能信号，地址信号等。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2005151323A Sampling frequency converting apparatus 有权
标题翻译：采样频率转换装置
公开(公告)号：JP2005151323A
公开(公告)日：2005-06-09
申请号：JP2003387986
申请日：2003-11-18
申请人： Yamaha Corp , ヤマハ株式会社
发明人： ICHIKI TETSUJI , SHIRAKAWA TOKIO
IPC分类号： H03H17/00 , H03H17/06 , H03M7/32
摘要： PROBLEM TO BE SOLVED: To convert a sampling frequency while dealing with frequency variations for arbitrary input and output sampling frequencies Fin, Fout.
SOLUTION: On the basis of input and output clocks CKin, CKout, Fin, Fout are measured and a multiplier MP is determined. The clock CKout is multiplied by the multiplier MP and a clock CKover is generated. A counter 204 counts CKin and the write address wad of input data Din is supplied to a FIFO 206. A full adder 218 accumulates a signal Delta (nearly Fin/Fover) for each CKover and generates a signal SH each time the result of the accumulation exceeds "1". A counter 202 outputs the result of counting the signal SH as a read address rad. A full adder 212 or the like finely adjusts the value of Delta on the basis of "wad-rad". A limit circuit 214 suppresses the value of Delta into a predetermined range on the basis of the measured value of Fin/Fout.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：在处理任意输入和输出采样频率Fin，Fout的频率变化时转换采样频率。
解决方案：根据输入和输出时钟CKin，CKout，Fin，Fout进行测量，并确定乘法器MP。时钟CKout乘以乘法器MP并产生时钟CKover。计数器204对CKin进行计数，并且将输入数据Din的写入地址数据提供给FIFO 206.全加器218对每个CKover累加一个信号Delta（几乎Fin / Fover），并且每次积累的结果产生一个信号SH 超过“1”。计数器202将对信号SH进行计数的结果输出为读地址rad。全加器212等基于“wad-rad”精确地调整Delta的值。限制电路214基于Fin / Fout的测量值来将Delta的值抑制在预定范围内。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2004109541A Musical sound synthesizer 有权
标题翻译：音乐合成器
公开(公告)号：JP2004109541A
公开(公告)日：2004-04-08
申请号：JP2002272482
申请日：2002-09-19
申请人： Yamaha Corp , ヤマハ株式会社
发明人： TAKEISHI EIICHI , ICHIKI TETSUJI
IPC分类号： G10H1/00 , G10H1/46 , G10H7/02
摘要： PROBLEM TO BE SOLVED: To detect abnormality of a word clock to generate an alarm with a simple configuration in a musical sound synthesizer such as a sound source board which operates synchronously with a word clock supplied from outside in every sampling cycle according to a system clock independent of the word clock. SOLUTION: A frequency dividing circuit 62 divides the frequency of a system clock SCLK by two and outputs a signal S1 having a frequency which is 1024 times as high as an ideal sampling frequency Fs. A cycle counter 64 counts this signal S1 and is reset in sampling cycles based upon the word clock WCK. A maximum value of the count value of the cycle counter 64 is stored in an M detection register 52. When the word clock WCK has ideal sampling cycles, the value stored in the M detection register 52 is "1023", but if an error occurs, the value stored in the M detection register 52 is "1023" or below or "1024" and above. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了检测字时钟的异常，以便在诸如在每个采样周期中从外部提供的字时钟同步操作的声源板等音乐声音合成器中，以简单的配置产生报警，根据独立于字时钟的系统时钟。解决方案：分频电路62将系统时钟SCLK的频率除以2，并输出具有与理想采样频率Fs的1024倍的频率的信号S1。循环计数器64对该信号S1进行计数，并且基于字时钟WCK以采样周期复位。周期计数器64的计数值的最大值存储在M检测寄存器52中。当字时钟WCK具有理想的采样周期时，存储在M检测寄存器52中的值为“1023”，但是如果发生错误存储在M检测寄存器52中的值为“1023”或更低或“1024”及以上。版权所有（C）2004，JPO

10. 发明专利

JP2003255945A MIXING DEVICE, MUSICAL SOUND GENERATING DEVICE AND LARGE- SCALE INTEGRATED CIRCUIT FOR MIXING 审中-公开
公开(公告)号：JP2003255945A
公开(公告)日：2003-09-10
申请号：JP2002055101
申请日：2002-02-28
申请人： YAMAHA CORP
发明人： ICHIKI TETSUJI , TAKEISHI EIICHI
IPC分类号： G10H1/02 , G10H1/46 , H04R3/00
摘要： PROBLEM TO BE SOLVED: To efficiently use the resource of an arithmetic operation for mixing. SOLUTION: A plurality of arithmetic operation channels for mixing are provided in a mixing device (210) which distributes the signals of a plurality of input channels to any one of a plurality of output channels and mixes them. In order to supply the signal of a given input channel to one or a plurality of specified output channels, an arbitrary input channel of an inputting source and an arbitrary output channel of an output destination are variably assigned to each arithmetic operation channel so as to use one arbitrary arithmetic operation channel or a plurality of arbitrary operation channels among the arithmetic operation channels. The arithmetic operation for mixing the signals of the input channels of the input source to the output channels of the output destination is performed in each operation channel in accordance with assignments. COPYRIGHT: (C)2003,JPO

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