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1. 发明专利

JP2000138201A METHOD AND SYSTEM FOR DRY ETCHING OF HALF-TONE PHASE SHIFTED FILM, HALF-TONE PHASE SHIFTED PHOTOMASK AND MANUFACTURE THEREOF, AND SEMICONDUCTOR CIRCUIT AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2000138201A
公开(公告)日：2000-05-16
申请号：JP30901098
申请日：1998-10-29
申请人： ULVAC SEIMAKU KK , MITSUBISHI ELECTRIC CORP
发明人： SASAKI TAKAHIDE , HARASHIMA NORIYUKI , AOYAMA SATORU , SAKAMOTO SHOICHI
IPC分类号： H01L21/302 , C23F4/00 , G03F1/32 , G03F1/68 , G03F1/80 , H01L21/306 , H01L21/3065 , G03F1/08
摘要： PROBLEM TO BE SOLVED: To reduce dimensional differences due to inconsistencies in pattern density in a plane by using a mixed gas, wherein a reducing gas is added to a reactive ion etching gas consisting of an oxygen-containing gas and a halogen- containing gas as a reactive etching gas. SOLUTION: A dry etching system (MERIE system) allows dry etching to a chromic half-tone phase shift film. At this time, a mixed gas wherein a gas containing at least hydrogen, such as H2, and HCl gas, is added to a halogen- containing gas such as Cl2+O2 is used. This enables dimensional control with in a plane which is equal to that of a mask wherein patterns are formed in generally uniform density in a plane, namely, which can extremely reduce dimensional differences in the design dimension of one to two μm wide, even in a chromic half-tone phase shift photomask, wherein film and rough patterns coexist within a plane.

2. 发明专利

JP2000114246A DRY ETCHING METHOD AND APPARATUS, PHOTORESIST MASK AND METHOD OF PRODUCING THE SAME, AND SEMICONDUCTOR CIRCUIT AND METHOD OF PRODUCING THE SAME 失效
公开(公告)号：JP2000114246A
公开(公告)日：2000-04-21
申请号：JP30900298
申请日：1998-10-29
申请人： ULVAC SEIMAKU KK , MITSUBISHI ELECTRIC CORP
发明人： SASAKI TAKAHIDE , HARASHIMA NORIYUKI , AOYAMA SATORU , SAKAMOTO SHOICHI
IPC分类号： H01L21/302 , G03F1/08 , G03F1/80 , G03F7/40 , H01L21/3065 , H01L21/3213 , H01L21/768
摘要： PROBLEM TO BE SOLVED: To reduce differences in dimension due to difference in pattern density on the surface by using a mixed gas, in which reducing gas is added to reactive etching gas consisting of oxygen containing gas and halogen containing gas in dry etching process of a metal thin film. SOLUTION: When patterning material of a substrate 11 on an RF electrode 10 is etched, an etching chamber 2 is evacuated by an vacuum system, and a mixed gas is introduced through reactive etching gas inlet 30 into the chamber 2 by a gas-supply system 16 comprising a gas cylinder and a massflow controller, the mixed gas in which reducing gas containing hydrogen is added to reactive etching gas which consists of oxygen containing gas and halogen containing gas. Two pairs of electromagnets 5, 6, 7, 8 is excited, and plasma is excited by applying RF power to the RF electrode 10. As a result, the difference in dimensions can be reduced due to the difference in pattern density on the surface of the substrate 11, and highly accurate photoresist mask can be obtained.

3. 发明专利

JP2004289391A Noise elimination circuit 审中-公开
标题翻译：噪声消除电路
公开(公告)号：JP2004289391A
公开(公告)日：2004-10-14
申请号：JP2003077756
申请日：2003-03-20
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： SAKAMOTO SHOICHI
IPC分类号： H03K5/1252 , H03K17/00 , H03K17/16
摘要： PROBLEM TO BE SOLVED: To provide a noise elimination circuit capable of eliminating noise with a simple configuration. SOLUTION: The noise elimination circuit is provided with: a full wave rectifier circuit 4 for receiving an input signal, applying full wave rectification to the input signal, converting a negative voltage side component of the input signal into a positive voltage side component and providing an output; differentiation circuits 3, 5 for outputting pulse signals in pair generated at both leading and trailing edges of a pulse signal at the output of the full wave rectifier circuit 4; a buffer gate 6 for detecting it when the pulse signal outputs in pairs from the differentiation circuits 3, 5 reach a prescribed gate detection voltage or over; and a shift register 7 for outputting a pulse signal whose level goes to an H by the pulse signal coming earlier in the pulse signals in pairs detected by the differentiation circuits 3, 5 and goes to an L by the pulse signal coming later. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供能够以简单配置消除噪声的噪声消除电路。解决方案：噪声消除电路设置有：全波整流电路4，用于接收输入信号，向输入信号施加全波整流，将输入信号的负电压侧分量转换为正电压侧分量并提供输出; 差分电路3,5，用于在全波整流电路4的输出处输出在脉冲信号的前沿和后沿产生的脉冲信号; 当差分电路3,5成对地输出脉冲信号时，进行检测的缓冲器门6达到规定的栅极检测电压以上; 以及移位寄存器7，用于通过由差分电路3,5所检测出的成对脉冲信号中较早的脉冲信号输出电平变为H的脉冲信号，并且由稍后的脉冲信号变为L。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2002343699A WAFER ALIGNMENT DEVICE AND METHOD OF CORRECTING THE WAFER ALIGNMENT 失效
公开(公告)号：JP2002343699A
公开(公告)日：2002-11-29
申请号：JP2001145081
申请日：2001-05-15
申请人： MITSUBISHI ELECTRIC CORP
发明人： SEKINO SHIRO , SAKAMOTO SHOICHI , IWAMOTO TAKESHI
IPC分类号： G01B11/00 , G03F9/00 , H01L21/027
摘要： PROBLEM TO BE SOLVED: To provide a wafer alignment device for correcting the displacement of wafer alignment which is attributable to asymmetry of the coverage of an interlayer film. SOLUTION: This wafer alignment device has a detection unit 1, which includes a CCD camera 2 for photographing an image 5 of an alignment mark 32, or a laser light source 3 that is irradiated on the alignment mark 32, with laser beams and a diffracted light detector 4 that detects laser beams 6 reflected and diffracted by the alignment mark 32, a signal-analyzing unit for obtaining a correction amount of alignment by analyzing the signal of the image photographed by the CCD camera 2 or a signal of the laser beams detected by the detector 4, and a stage control unit 8 for controlling movement of a stage, on which a wafer 31 is placed based on the signal-analyzing unit 7.

5. 发明专利

JPH04170216A FILTER CIRCUIT 失效
公开(公告)号：JPH04170216A
公开(公告)日：1992-06-17
申请号：JP29819390
申请日：1990-11-02
申请人： MITSUBISHI ELECTRIC CORP
发明人： SAKAMOTO SHOICHI
IPC分类号： H03K5/1252 , H03K5/01
摘要： PURPOSE:To prevent malfunction by extending the pulse width of a pulse signal outputted from a constant period pulse generating means, limiting an input with an AND means between the pulse signal and a logic signal, and inputting the output of the AND means to a logic IC. CONSTITUTION:An input logic signal is fetched to the circuit as a pulse signal of a constant period. A parameter of a time constant is adjusted in advance so that the period is identical to the output pulse period outputted from a pulse generation IC 11 receiving a pulse waveform depending on a time constant comprising an input resistor 8 and a feedback capacitor 9 of an integration circuit IC 7 and on the voltage of a reference voltage 10. The output of the pulse generation IC 11 is the trigger signal of a one-shot multivibrator circuit 5 and the pulse for a prescribed time t1 is fed to a 2-input AND element 6. When the pulse width of the input logic signal is overlapped onto the pulse width of a prescribed time, a logic signal is outputted at the output of the 2-input AND element 6. Thus, noise is eliminated and malfunction is prevented.

6. 发明专利

JP2004158523A Method for measuring thickness of buried material, method for regulating thickness of buried material using the same, and method for manufacturing semiconductor device 审中-公开
公开(公告)号：JP2004158523A
公开(公告)日：2004-06-03
申请号：JP2002320803
申请日：2002-11-05
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： SAKAMOTO SHOICHI , YOSHIKAWA KAZUNORI
IPC分类号： H01L21/66
摘要： PROBLEM TO BE SOLVED: To obtain a method for measuring the thickness of a buried material without cutting a semiconductor substrate.
SOLUTION: The method for measuring the thickness of the material buried in a first recess in a dual damascene process includes the steps of providing a first recess toward the first wiring on an interlayer insulating film provided on the first wiring on the semiconductor substrate, filling the material in the recess, then forming a recess for second wiring and a recess for connecting the first and second wiring from the first recess by etching the interlayer insulating film and the buried material, and forming multilayer wiring. The opening width (e), the depth (h) and the width (f) of the bottom of the first recess when the section of the first recess is formed in a forward tapered shape and the first recess is empty, and the surface width (g) of the surface of the buried material are measured so that the respective measuring line segments are included in the section of the same recess. The thickness (d) of the buried material in the first recess is calculated by formula (1): d=h×(g-f)÷(e-f).
COPYRIGHT: (C)2004,JPO

7. 发明专利

JPH06148864A PHASE SHIFT MASK AND ITS PRODUCTION 失效
公开(公告)号：JPH06148864A
公开(公告)日：1994-05-27
申请号：JP29834892
申请日：1992-11-09
申请人： RYODEN SEMICONDUCTOR SYST ENG , MITSUBISHI ELECTRIC CORP
发明人： TANAKA SHINICHIRO , SAKAMOTO SHOICHI
IPC分类号： G03F1/32 , G03F1/68 , G03F1/80 , H01L21/027 , H01L21/30 , G03F1/08
摘要： PURPOSE:To easily form the phase shift mask having high accuracy by forming shifter films only in the fine pattern parts. CONSTITUTION:An etching stopper layer 2 is formed on a glass substrate y and after the shifter film (for example, SOG) 3 is applied thereon, an electron beam negative type resist 4 is applied thereon. This resist is subjected to electron beam exposing then to developing. The shifter film 3 of the peripheral circuit pattern parts is etched off with these resist patterns as a mask. The resist is then subjected to electron beam exposing then to developing and with such resist patterns as a mask, a semi-transmissive light shielding film 5 is etched; in succession, the shifter films 3 are etched and finally an electron beam positive type resist 6 is peeled. The shifter films of the peripheral circuit pattern parts of the phase shift mask where a transfer margin is not so much requested are removed in such a manner, by which the shifter films 3 are provided only in the fine pattern parts.

8. 发明专利

JPS62271009A FUNCTION GENERATOR WITH ADDRESS DIRECT DESIGNATING MEMORY 失效
公开(公告)号：JPS62271009A
公开(公告)日：1987-11-25
申请号：JP11635986
申请日：1986-05-19
申请人： MITSUBISHI ELECTRIC CORP
发明人： SAKAMOTO SHOICHI
IPC分类号： G06F1/02
摘要： PURPOSE:To extremely simplify the constitution of a function generating device together with a big reduction of cost, by using the digital value received from an A/D converter as it is as an address designating signal of a memory. CONSTITUTION:The output digital value serving as a function corresponding to the digital value supplied from an A/D converter 1 is previously stored in a memory area where said input digital value is an address. The analog input signal is converted into the digital value by the converter 1. This digital value is supplied directly to an address bus line 6 of a memory 3 and used as the data to designate an address of a memory area in the memory 3. Then the data stored in the designated address is taken out of the memory 3 as the output digital value and outputted to a D/A converter 4 to be converted into the analog output signal for output. In such a way, a desired function is produced with no use of a microprocessor and therefore the constitution a function generating device is extremely simplified together with a big reduction of cost.

9. 发明专利

JP2009098019A Timing circuit 审中-公开
标题翻译：时序电路
公开(公告)号：JP2009098019A
公开(公告)日：2009-05-07
申请号：JP2007270419
申请日：2007-10-17
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： SAKAMOTO SHOICHI
IPC分类号： G01R29/02
摘要： PROBLEM TO BE SOLVED: To obtain a timing circuit for preventing a period of a clock signal from being limited, and timing a narrow to-be-measured pulse width.
SOLUTION: A plurality of counters 3A, 3B, 3C are provided so as to count the clock signal while the to-be-measured pulse signal is a logic H. The respective counters 3A, 3B, 3C are input by the clock signal generated by a clock circuit 2 or its delayed version through a delay element, and also input by a logic signal obtained by converting the to-be-measured pulse signal by a buffer circuit 1. The respective counters 3A, 3B, 3C count the clock signal during the logic H. From the counted value, the narrow to-be-measured pulse width can be timed by obtaining a time based on a count value calculated by a calculation circuit 5.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：获得用于防止时钟信号的周期被限制的定时电路，以及定时窄的待测脉冲宽度。
解决方案：多个计数器3A，3B，3C被设置为在待测脉冲信号为逻辑H的同时对时钟信号进行计数。相应的计数器3A，3B，3C由时钟通过延迟元件由时钟电路2产生的信号或其延迟版本，并且还由通过缓冲电路1转换待测脉冲信号而获得的逻辑信号输入。各个计数器3A，3B，3C对时钟信号。从计数值来看，可以通过基于由计算电路5计算的计数值获得时间来计时窄测量脉冲宽度。（C）2009年， JPO和INPIT

10. 发明专利

JP2005354855A Rush current suppressing circuit 审中-公开
标题翻译： RUSH电流抑制电路
公开(公告)号：JP2005354855A
公开(公告)日：2005-12-22
申请号：JP2004175311
申请日：2004-06-14
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： SAKAMOTO SHOICHI
IPC分类号： H02H9/02 , G05F1/10 , H02J1/00
摘要： PROBLEM TO BE SOLVED: To obtain a rush current suppressing circuit that can suppress a rush current that occurs to a load circuit by a simple circuit structure when a power supply source is turned on. SOLUTION: This circuit is constituted of a transistor 4 whose emitter and collector are connected between the output side of the power supply source 2 and the input side of a load circuit 5, an operation circuit 6 that supplies a base current to the transistor 4 between the output side of the power supply source 2 and the base of the transistor 4 by turning on the power supply source 2 to operate the transistor 4, and a base current control circuit 7 that controls the base current at the base of the transistor 4. COPYRIGHT: (C)2006,JPO&NCIPI

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