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1. 发明专利

JP2015046507A ＥＳＤ保護回路审中-公开
标题翻译： ESD保护电路
公开(公告)号：JP2015046507A
公开(公告)日：2015-03-12
申请号：JP2013177168
申请日：2013-08-28
申请人：株式会社東芝 , Toshiba Corp
发明人： WAKITA NAOKI , YANO MITSUHIRO , NISHIMOTO RYUJI , MURATA KATSUHIKO
IPC分类号： H01L27/06 , H01L21/822 , H01L27/04 , H01L29/861 , H01L29/868 , H03K19/003
CPC分类号： H02H9/046 , H02H9/043
摘要：【課題】消費電流を低減することが可能なESD保護回路を提供する。【解決手段】ESD保護回路は、電源線と接地線との間に接続され、電源線に流れる電流を検出し、この検出結果に応じた制御信号を出力する検知制御回路を備える。ESD保護回路は、ドレインが電源線に接続され、ゲートに制御信号が供給される保護用nMOSトランジスタを備える。ESD保護回路は、アノードが保護用nMOSトランジスタのソースに接続され、カソードが接地線に接続された1個のPN接合ダイオードを備える。【選択図】図1
摘要翻译：要解决的问题：提供一种能够抑制电流消耗的ESD保护电路。解决方案：ESD保护电路包括连接在电力线和接地线之间的检测控制电路，检测通过电力线的电流，输出与检测结果对应的控制信号。 ESD保护电路包括用于保护的nMOS晶体管，其漏极与电源线连接，并且其栅极被提供控制信号。 ESD保护电路包括一个PN结二极管，其阳极与nMOS晶体管的源极连接，用于保护，其阴极与地线连接。

2. 发明专利

JP2003022952A Drawing data generating system, drawing data generating method, drawing data generating program, method for producing reticle and method for fabricating semiconductor device 审中-公开
标题翻译：绘制数据生成系统，绘制数据生成方法，绘制数据生成程序，生产方法和制造半导体器件的方法
公开(公告)号：JP2003022952A
公开(公告)日：2003-01-24
申请号：JP2001206541
申请日：2001-07-06
申请人： Toshiba Corp , 株式会社東芝
发明人： WATANABE SUSUMU , YANO MITSUHIRO
IPC分类号： G03F1/68 , G03F1/70 , G03F7/20 , H01L21/027 , G03F1/08
CPC分类号： G03F1/00
摘要： PROBLEM TO BE SOLVED: To generate mask drawing data in which the number of master masks to be generated can be minimized.
SOLUTION: The method for generating drawing data comprises a step (S101) for generating chip division information by dividing a chip pattern such that pattern data obtained by enlarging the chip pattern data of a reticle is contained in the drawing area of a master mask, generating chip layout information of the master mask by assigning the division patterns in the chip division information sequentially to the master mask in the ascending order and registering the chip layout information in a master mask chip layout information memory, a step (S102) for generating the chip pattern data of the master mask by dividing each chip according to the chip layout information of the master mask with reference to the chip pattern data of the reticle and registering the chip pattern data of the master mask in a master mask pattern data memory, and a step (S103) for generating master mask drawing data with reference to the chip layout information of the master mask and the chip pattern data of the master mask.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：生成可以使生成的主掩模的数量最小化的掩模绘图数据。解决方案：用于生成绘图数据的方法包括：步骤（S101），用于通过划分芯片模式来产生芯片分割信息，使得通过将掩模版的芯片图案数据放大而获得的图案数据包含在主掩模的绘图区域中，产生通过将芯片划分信息中的划分模式按升序顺序地分配给主掩模，并将芯片布局信息登记在主掩模芯片布局信息存储器中，将主芯片的芯片布局信息分配给主掩模，步骤（S102）通过参照掩模版的芯片图案数据，根据主掩模的芯片布局信息划分每个芯片并将主掩模的芯片图案数据登记在主掩模图案数据存储器中，从而分割主掩模的图案数据，以及步骤（S103），用于参照主掩模的芯片布局信息和芯片图案数据生成主掩模绘制数据主面具。

3. 发明专利

JP2002197130A METHOD AND DEVICE FOR PROCESSING DESIGN PATTERN DATA OF SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2002197130A
公开(公告)日：2002-07-12
申请号：JP2000398670
申请日：2000-12-27
申请人： TOSHIBA CORP
发明人： YANO MITSUHIRO , WATANABE SUSUMU
IPC分类号： G03F1/68 , G03F1/70 , G06F17/50 , H01L21/82 , G03F1/08
摘要： PROBLEM TO BE SOLVED: To efficiently conduct a graphic arithmetic processing about pattern data such as a system LSI wherein a range obeying a hierarchical restriction and a range not obeying the hierarchical restriction are mixed. SOLUTION: The range not obeying the hierarchical restriction of a design pattern of a semiconductor integrated circuit and the range obeying the hierarchical restriction of a memory part are divided, and each divided range is subjected to either one suitable graphic arithmetic processing of a hierarchical processing or a flat processing. Therefore, the graphic arithmetic processing can be carried out about pattern data such as a system LSI wherein a range obeying the hierarchical restriction and a range not obeying the hierarchical restriction are mixed.

4. 发明专利

JP2003195473A METHOD FOR CORRECTING PATTERN AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003195473A
公开(公告)日：2003-07-09
申请号：JP2001398438
申请日：2001-12-27
申请人： TOSHIBA CORP
发明人： KOBAYASHI SACHIKO , KOTANI TOSHIYA , TANAKA SATOSHI , WATANABE SUSUMU , YANO MITSUHIRO
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G03F7/20 , G06F17/50 , H01L21/027 , G03F1/08
摘要： PROBLEM TO BE SOLVED: To correct a design pattern to a shape suited to mask plotting or inspection by simple processing. SOLUTION: In a pattern correcting method to be executed by a computer, 1st correction for sides satisfying a prescribed condition out of sides constituting a designed pattern is performed by calculating correction values obtained considering an optical proximity effect. Then 2nd correction for sides not satisfying the prescribed condition is performed by using the correction value of the side adjacent to the side not satisfying the prescribed condition out of the sides corrected by the 1st correction and the sides corrected by the 1st correction are connected to each other with a segment. COPYRIGHT: (C)2003,JPO

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