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1. 发明专利

JP2014052652A Mask pattern data creation method, mask pattern data creation program, mask, and semiconductor device manufacturing method 有权
标题翻译：掩模图形数据创建方法，掩模图形数据创建程序，掩模和半导体器件制造方法
公开(公告)号：JP2014052652A
公开(公告)日：2014-03-20
申请号：JP2013224798
申请日：2013-10-29
申请人： Toshiba Corp , 株式会社東芝
发明人： KODAMA CHIKAAKI , ICHIKAWA HIROTAKA , KOTANI TOSHIYA , MASUKAWA KAZUYUKI
IPC分类号： G03F1/70 , G03F1/36 , H01L21/027
摘要： PROBLEM TO BE SOLVED: To provide a mask pattern data creation method capable of creating a high-accuracy pattern.SOLUTION: An auxiliary pattern which is created corresponding to a plurality of main patterns to be transferred to an object to be transferred to by exposure through a mask with the mask is not transferred to the object to be transferred to. The mask pattern data creation method for creating auxiliary pattern data corresponding to the auxiliary pattern includes arranging the auxiliary pattern data on a basis of the relation between the positional data and the size data of the auxiliary pattern data for at least one of the neighboring main pattern data determined corresponding to the clearance between the neighboring main pattern data.
摘要翻译：要解决的问题：提供能够创建高精度图案的掩模图案数据创建方法。解决方案：对应于要传送到要通过曝光传送的对象的多个主图案而创建的辅助图案具有掩模的掩模不转移到要传输的对象。用于创建与辅助图案相对应的辅助图案数据的掩模图案数据创建方法包括基于相邻主图案中的至少一个的辅助图案数据的位置数据和尺寸数据之间的关系布置辅助图案数据对应于相邻主图案数据之间的间隙确定的数据。

2. 发明专利

JP2014006392A Photomask coverage factor adjustment method and exposure method 审中-公开
标题翻译：光电覆盖因子调整方法和曝光方法
公开(公告)号：JP2014006392A
公开(公告)日：2014-01-16
申请号：JP2012142160
申请日：2012-06-25
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAZAWA TAKASHI , KOTANI TOSHIYA , TAGUCHI TAKAFUMI , OBARA TAKASHI
IPC分类号： G03F1/70 , H01L21/027
摘要： PROBLEM TO BE SOLVED: To adjust a photomask coverage factor within a desired range without transferring an unnecessary pattern onto a wafer.SOLUTION: A photomask coverage factor adjustment method includes the steps of: calculating a distribution of a coverage factor that is a ratio of a circuit pattern formed in a predetermined region to layout data of a photomask having the circuit pattern to be transferred onto a wafer; and adjusting a whole coverage factor including an auxiliary pattern within a desired range by disposing the auxiliary pattern that is not resolved on the wafer by exposure using the photomask in a region where the circuit pattern is not present on the photomask on the basis of the calculated distribution of the coverage factor.
摘要翻译：要解决的问题：将光掩模覆盖因子调整到所需范围内，而不会将不必要的图案转移到晶片上。解决方案：光掩模覆盖因子调整方法包括以下步骤：计算覆盖因子的分布，形成在预定区域中的电路图案，以布置具有要转印到晶片上的电路图案的光掩模的数据; 并且通过在所述光掩模上不存在所述电路图案的区域中，通过使用所述光掩模进行曝光来设置在所述晶片上未分辨的辅助图案，从而将包括辅助图案的整体覆盖率调整在期望范围内分布覆盖因子。

3. 发明专利

JP2012198411A Mask pattern correction method, mask pattern correction program, and method of manufacturing semiconductor device 有权
标题翻译：掩模图案校正方法，掩模图案校正程序和制造半导体器件的方法
公开(公告)号：JP2012198411A
公开(公告)日：2012-10-18
申请号：JP2011062841
申请日：2011-03-22
申请人： Toshiba Corp , 株式会社東芝
发明人： UNO TAIGA , KOTANI TOSHIYA , MASHITA HIROMITSU , ARISAWA YUKIYASU
IPC分类号： G03F1/68 , G03F1/22 , H01L21/027
CPC分类号： G03F1/36 , G03F1/70 , G03F7/70441 , G03F7/70941
摘要： PROBLEM TO BE SOLVED: To provide a mask pattern correction method capable of performing a mask pattern correction with flare taken into consideration, at high speed and at high accuracy.SOLUTION: In a mask pattern correction method according to an embodiment, a mask pattern correction amount for a reference flare value is calculated as a reference mask correction amount for every type of pattern within a layout, and a change amount of the mask pattern correction amount corresponding to a change amount of a flare value is calculated as change amount information. Then, the reference mask correction amount and the change amount information are extracted corresponding to the pattern from association information in which the pattern, the reference mask correction amount, and the change information are associated with each other. A mask pattern corresponding to the flare value of the pattern is created based on a flare difference which is a difference between the flare value in an arrangement position at which the pattern is disposed and the reference flare value and based on the extracted reference mask correction amount and the extracted change amount information.
摘要翻译：要解决的问题：提供能够以高速和高精度考虑在考虑中进行掩模图案校正的掩模图案校正方法。解决方案：在根据实施例的掩模图案校正方法中，将用于参考闪光值的掩模图案校正量计算为布局内的每种图案的基准掩模校正量，并且掩模的改变量将与闪光值的变化量对应的图案校正量计算为变化量信息。然后，根据图案，参考掩模修正量和变更信息相关联的关联信息，对应于图案提取参考掩模修正量和变化量信息。基于作为布置图案的布置位置中的闪光值与参考闪光值之间的差的闪光差，并且基于提取的基准掩膜校正量，创建与图案的闪光值相对应的掩模图案和提取的改变量信息。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2012064898A Exposure method and method of manufacturing semiconductor device 审中-公开
标题翻译：曝光方法和制造半导体器件的方法
公开(公告)号：JP2012064898A
公开(公告)日：2012-03-29
申请号：JP2010210125
申请日：2010-09-17
申请人： Toshiba Corp , 株式会社東芝
发明人： HASHIMOTO TAKAKI , FUKUHARA KAZUYA , KOTANI TOSHIYA , KAI YASUNOBU
IPC分类号： H01L21/027 , G03F1/70
CPC分类号： H01L27/0207 , G03F1/50 , G03F7/70325 , H01L21/0274 , H01L21/31144 , H01L27/11519 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To provide an exposure method which can ensure high integration of a semiconductor device, and to provide a method of manufacturing a semiconductor device.SOLUTION: In the exposure method, a photomask is irradiated with light by lighting, diffraction light exiting the photomask is condensed by means of a lens, and multiple spot images are focused on the exposure surface. In the photomask, light transmission regions are formed at lattice points represented by unit lattice vectors which do not intersect perpendicularly to each other. Light-emitting regions are set by the lighting so that three or more diffraction light beams pass through positions equidistant from the center of the pupil of the lens.
摘要翻译：要解决的问题：提供一种能够确保半导体器件的高集成度的曝光方法，并提供制造半导体器件的方法。解决方案：在曝光方法中，光照照射光掩模，离开光掩模的衍射光通过透镜聚光，并且多个斑点图像聚焦在曝光表面上。在光掩模中，光透射区域形成在不与彼此垂直相交的单位晶格矢量表示的格点处。通过照明设定发光区域，使得三个以上的衍射光束通过与透镜的光瞳的中心等距的位置。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2012043942A Light exposure parameter deciding device, light exposure system, check system, and light exposure parameter deciding method 审中-公开
标题翻译：光照曝光参数决定装置，曝光系统，检查系统和光照曝光参数决定方法
公开(公告)号：JP2012043942A
公开(公告)日：2012-03-01
申请号：JP2010183158
申请日：2010-08-18
申请人： Toshiba Corp , 株式会社東芝
发明人： KOTANI TOSHIYA , TAKIMOTO MICHIYA
IPC分类号： H01L21/027
摘要： PROBLEM TO BE SOLVED: To provide a light exposure parameter deciding device capable of improving size uniformity of a pattern, a light exposure system, a check system, and a light exposure parameter deciding method.SOLUTION: A light exposure parameter deciding device comprises a simulation execution part 112 for executing a lithography simulation using light strength information and a predetermined light exposure parameter corresponding to a plurality of regions on a light exposure mask and calculating a prediction pattern shape; and an evaluation value calculation part 113 for calculating an evaluation value of the prediction pattern shape. The light exposure parameter deciding device 100 repeats change of the light exposure parameter, and execution of the lithography simulation using the changed light exposure parameter until the evaluation value falls in a predetermined tolerance, and allocates the light exposure parameter to the region.
摘要翻译：要解决的问题：提供能够改善图案的尺寸均匀性，曝光系统，检查系统和曝光参数确定方法的曝光参数确定装置。曝光参数确定装置包括：模拟执行部分112，用于使用光强度信息和对应于曝光掩模上的多个区域的预定曝光参数来执行光刻模拟并计算预测图案形状; 以及评估值计算部113，用于计算预测图案形状的评估值。曝光参数确定装置100重复曝光参数的改变，以及使用改变的曝光参数执行光刻模拟，直到评估值落在预定的公差内，并将曝光参数分配给该区域。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2011066337A Method of manufacturing nonvolatile semiconductor storage device, and nonvolatile semiconductor storage device 审中-公开
标题翻译：制造非易失性半导体存储器件的方法和非易失性半导体存储器件
公开(公告)号：JP2011066337A
公开(公告)日：2011-03-31
申请号：JP2009217787
申请日：2009-09-18
申请人： Toshiba Corp , 株式会社東芝
发明人： YUDA RYOTA , KOTANI TOSHIYA , TAGUCHI TAKAFUMI , KODAMA CHIKAAKI
IPC分类号： H01L27/10 , H01L21/3205 , H01L21/8246 , H01L23/52 , H01L27/105 , H01L27/28 , H01L45/00 , H01L49/00 , H01L51/05
CPC分类号： H01L27/2481 , G11C5/02 , G11C11/161 , G11C11/1659 , G11C11/22 , G11C13/0004 , H01L27/0203 , H01L27/0207 , H01L27/1021 , H01L27/2409 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a nonvolatile semiconductor storage device that prevents occurrence of a short circuit among a plurality of columnar memory cells having a laminate structure. SOLUTION: The method of manufacturing the nonvolatile semiconductor storage device includes the processes of: forming the plurality of columnar memory cells MC arranged in a matrix form; forming word lines 47a, 47c and 47e which come into contact with one-side bottom surfaces of groups of memory cells arrayed in straight lines and parallel to one another; and forming bit lines 56b, 56d which come into contact with other-side bottom surfaces of groups of memory cells arrayed in straight lines and parallel to one another, and cross the word lines in plan view. In the process of forming the word lines, dummy cells DMC1, DMC2 are formed which are arranged at predetermined intervals with end-part memory cells MCe1, MCe3 positioned at end parts of the groups of memory cells coming into contact with the same word lines or bit lines among the plurality of memory cells, and have the same laminate structure as that of the memory cells MC. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供一种制造非易失性半导体存储装置的方法，其防止在具有层叠结构的多个柱状存储单元之间发生短路。解决方案：制造非易失性半导体存储装置的方法包括以下处理：形成以矩阵形式布置的多个柱状存储单元MC; 形成与直线排列并且彼此平行的存储单元组的一侧底面接触的字线47a，47c和47e; 并且形成与排列成直线并且彼此平行的存储单元组的另一侧底面接触的位线56b，56d，并且在平面图中与字线交叉。在形成字线的过程中，形成以预定间隔布置的终端部分存储单元MCe1，MCe3位于与相同字线接触的存储器单元组的端部的虚拟单元DMC1，DMC2，并且具有与存储单元MC相同的层叠结构。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2011003644A Lithography simulation method, and program 审中-公开
标题翻译： LITHOGRAPHY模拟方法和程序
公开(公告)号：JP2011003644A
公开(公告)日：2011-01-06
申请号：JP2009144202
申请日：2009-06-17
申请人： Toshiba Corp , 株式会社東芝
发明人： FUKUHARA KAZUYA , KOTANI TOSHIYA
IPC分类号： H01L21/027 , G03F1/36 , G03F1/68
摘要： PROBLEM TO BE SOLVED: To easily execute accurate lithography simulation considering a best focus difference.SOLUTION: The lithography simulation method includes steps of: applying defocus processing to an image formation condition of lithography simulation by referring to a table with a relationship between the dimension of a mask pattern of a simulation object and a defocus amount specified therein; and calculating the dimension of a transfer pattern corresponding to the mask pattern using the image formation condition with the defocus processing applied thereto.
摘要翻译：要解决的问题：考虑到最佳聚焦差异，轻松执行精确的光刻模拟。解决方案：光刻模拟方法包括以下步骤：通过参考具有尺寸之间的关系的表格将散焦处理应用于光刻模拟的图像形成条件模拟对象的掩模图案和其中指定的散焦量; 以及使用应用了散焦处理的图像形成条件来计算与掩模图案对应的传送图案的尺寸。

8. 发明专利

JP2010079063A Pattern formation defective area calculating method and pattern layout evaluating method 有权
标题翻译：模式形成缺陷区计算方法和模式布局评估方法
公开(公告)号：JP2010079063A
公开(公告)日：2010-04-08
申请号：JP2008248785
申请日：2008-09-26
申请人： Toshiba Corp , 株式会社東芝
发明人： TAKAHASHI MASANORI , KOTANI TOSHIYA , TANAKA SATOSHI
IPC分类号： G03F1/68 , G03F1/70 , G03F1/84 , H01L21/027 , H01L21/82
CPC分类号： G06F17/5081
摘要： PROBLEM TO BE SOLVED: To provide an exposure defective area calculating method of accurately calculating a pattern formation detective area, caused by a step pattern in a step pattern layout plane, in a short time. SOLUTION: Correspondence relation between the distance from a pattern of a gate G1, in the substrate plane and information regarding a possibility of an exposure defective area; a layout used for pattern formation of a gate G1 are used to calculate, as a defect occurrence risk degree map 21; and an area where a pillar pattern P has a pattern formation defect, when the pillar pattern P is formed after the gate G1, after the gate G1 is formed as the step pattern on the substrate. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种在短时间内精确地计算由步进图案布局平面中的台阶图案引起的图案形成检测区域的曝光缺陷区域计算方法。＆lt; P＆gt;解决方案：从基板平面中的栅极G1的图案的距离和关于曝光缺陷区域的可能性的信息之间的对应关系; 使用用于门G1的图案形成的布局作为缺陷发生风险度映射21来计算; 以及在栅极G1形成为基板上的台阶图形之后，当在栅极G1之后形成柱状图案P时，柱状图案P具有图案形成缺陷的区域。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2009251500A Method of verifying pattern, method of forming pattern, method of manufacturing semiconductor device, and program 审中-公开
标题翻译：验证图案的方法，形成图案的方法，制造半导体器件的方法和程序
公开(公告)号：JP2009251500A
公开(公告)日：2009-10-29
申请号：JP2008102381
申请日：2008-04-10
申请人： Toshiba Corp , 株式会社東芝
发明人： KOTANI TOSHIYA , MASHITA HIROMITSU , KOBAYASHI KAZUTO
IPC分类号： G03F1/68 , G03F1/70 , H01L21/027
CPC分类号： G03F1/36 , G03F1/68
摘要： PROBLEM TO BE SOLVED: To provide a method of verifying a pattern, a method of forming the pattern, a method of manufacturing a semiconductor device, and a program such that the size of the pattern is efficiently measured to improve size guarantee precision of the pattern. SOLUTION: The method of verifying the pattern includes, dividing a pattern data region or a pattern formation region formed based on the pattern data to a plurality of unit regions, calculating a pattern area ratio with respect to each unit region, calculating differences in the amount of the pattern area ratio between each unit region and adjacent unit regions thereto, setting the measurement points with the number or density corresponding to the difference in the amount of pattern area ratio for each unit region with respect to the pattern of the pattern formation region, measuring the pattern size at each measurement point, and verifying whether the size measurement value satisfies predetermined conditions or not. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种验证图案的方法，形成图案的方法，制造半导体器件的方法和程序，使得有效地测量图案的尺寸以提高尺寸保证精度的模式。解决方案：验证图案的方法包括：将基于图案数据形成的图案数据区域或图案形成区域划分为多个单位区域，计算相对于每个单位区域的图案面积比，计算差异在每个单位区域和相邻单元区域之间的图案面积比的量中，对于每个单位区域的图案面积比的量对应于与图案的图案相对应的数量或密度的测量点形成区域，测量每个测量点处的图案尺寸，以及验证尺寸测量值是否满足预定条件。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2009175262A Mask pattern verification method and program 审中-公开
标题翻译：掩模图形验证方法和程序
公开(公告)号：JP2009175262A
公开(公告)日：2009-08-06
申请号：JP2008011725
申请日：2008-01-22
申请人： Toshiba Corp , Toshiba Memory Systems Co Ltd , 東芝メモリシステムズ株式会社 , 株式会社東芝
发明人： KODAMA CHIKAAKI , ICHIKAWA HIROTAKA , KOTANI TOSHIYA , MASHITA HIROMITSU , NAKAJIMA FUMIHARU
IPC分类号： G03F1/84 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To accurately verify whether L/S (line and space widths) of each line pattern on a mask data agrees with the specification of a mask layout design. SOLUTION: Whether mask pattern data are right or not is verified by comparing the L/S obtained by measuring a dimension in each line pattern group with a L/S pattern specification table. COPYRIGHT: (C)2009,JPO&INPIT

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