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1. 发明专利

JP2012114226A Manufacturing method of nonvolatile semiconductor memory device 审中-公开
标题翻译：非线性半导体存储器件的制造方法
公开(公告)号：JP2012114226A
公开(公告)日：2012-06-14
申请号：JP2010261634
申请日：2010-11-24
申请人： Toshiba Corp , 株式会社東芝
发明人： WATANABE KATSURA , NAKAO SHINICHI , OTSUKA KENICHI
IPC分类号： H01L27/105 , H01L45/00 , H01L51/05 , H01L51/30
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a nonvolatile semiconductor memory device capable of suppressing power consumption and reducing switch malfunctions using a carbon nanotube as a variable resistive element.SOLUTION: A manufacturing method of a nonvolatile semiconductor memory device of an embodiment includes: a step of forming a lower electrode on a semiconductor substrate 9; a step of forming a variable resistance layer 11 containing a carbon nanotube on the lower electrode; an irradiation step of irradiating the variable resistance layer with an electron beam or a photon beam; and a step of forming an upper electrode on the variable resistance layer after the irradiation step.
摘要翻译：解决的问题：提供一种能够抑制功耗并减少使用碳纳米管作为可变电阻元件的开关故障的非易失性半导体存储器件的制造方法。解决方案：实施例的非易失性半导体存储器件的制造方法包括：在半导体衬底9上形成下电极的步骤; 在下电极上形成含有碳纳米管的可变电阻层11的工序; 照射步骤，用电子束或光子束照射可变电阻层; 以及在照射步骤之后在可变电阻层上形成上电极的步骤。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2011135050A Nonvolatile semiconductor storage device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2011135050A
公开(公告)日：2011-07-07
申请号：JP2010251759
申请日：2010-11-10
申请人： Toshiba Corp , 株式会社東芝
发明人： KUBOI SHUICHI , TAKADA SHINTETSU , NAKAI TSUKASA , FUKUMIZU HIROYUKI , NOJIRI YASUHIRO , OTSUKA KENICHI
IPC分类号： H01L27/105 , G11C13/00 , H01L45/00 , H01L49/00
CPC分类号： H01L27/101 , H01L27/2409 , H01L45/04 , H01L45/148
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device that suppresses a probability of malfunction and is reducible in power consumption. SOLUTION: The nonvolatile semiconductor storage device includes a first wiring; a second wiring that exists at positions opposed to the first wiring; and a variable resistance layer that exists between the first wiring and the second wiring, and that can change reversibly between a first state having a first resistivity and a second state having a second resistivity that is higher than the first resistivity, by a voltage applied via the first wiring and the second wiring, or by a current supplied via the first wiring and the second wiring. The variable resistance layer has a compound of carbon and silicon as the main ingredient thereof, and also contains hydrogen. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种抑制故障概率并可减少功耗的非易失性半导体存储装置。解决方案：非易失性半导体存储装置包括第一布线; 存在于与所述第一布线相对的位置处的第二布线; 以及可变电阻层，其存在于所述第一布线和所述第二布线之间，并且可以在具有第一电阻率的第一状态和具有高于所述第一电阻率的第二电阻率的第二状态之间可逆地改变，第一布线和第二布线，或通过经由第一布线和第二布线提供的电流。可变电阻层具有碳和硅作为其主要成分的化合物，并且还含有氢。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2011142262A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2011142262A
公开(公告)日：2011-07-21
申请号：JP2010002924
申请日：2010-01-08
申请人： Toshiba Corp , 株式会社東芝
发明人： WATANABE KATSURA , OTSUKA KENICHI
IPC分类号： H01L31/10 , C23C16/24 , H01L21/3065 , H01L21/308 , H01L21/316 , H01L21/318
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device forming an antireflection structure on a predetermined layer surface by a simpler method. SOLUTION: The method of manufacturing the semiconductor device includes a step (S102) of forming a silicon(Si)-containing insulating film on a substrate in a high frequency power applied plasma atmosphere, a step (S104) of reducing output of the high frequency power while continuously flowing gas used in formation of the Si-containing insulating film to deposit a plurality of particles containing Si as a principal component on the Si-containing insulating film, and a step (S106) of etching the Si-containing insulating film using the plurality of particles as a mask. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过更简单的方法在预定的层表面上形成形成抗反射结构的半导体器件的方法。解决方案：制造半导体器件的方法包括在高频电力施加等离子体气氛中在衬底上形成含硅（Si）的绝缘膜的步骤（S102），步骤（S104），其降低在形成含Si绝缘膜的同时持续流动用于在含Si绝缘膜上沉积含有Si作为主要成分的多个粒子的气体的高频功率，以及蚀刻含Si的绝缘膜的步骤（S106）使用多个颗粒作为掩模的绝缘膜。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2010141046A Nonvolatile semiconductor memory and semiconductor memory device 审中-公开
标题翻译：非线性半导体存储器和半导体存储器件
公开(公告)号：JP2010141046A
公开(公告)日：2010-06-24
申请号：JP2008314761
申请日：2008-12-10
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAI TSUKASA , FUKUMIZU HIROYUKI , NOJIRI YASUHIRO , YAHIRO KAZUYUKI , OTSUKA KENICHI
IPC分类号： H01L27/10 , H01L45/00 , H01L49/00
摘要： PROBLEM TO BE SOLVED: To acquire high recording density and low power consumption operation, and to reduce a probability of incorrect switching.
SOLUTION: This nonvolatile semiconductor memory includes a resistance changing film 62 whose electric resistivity is changed according to the application of a voltage or a current, and electrodes 61 and 64 which are so provided as to sandwich the resistance changing film 62 in the film thickness direction. The resistance changing film 62 is formed by dissolving at least one kind of an additional element selected out of hydrogen, boron, nitrogen, fluorine, silicon and titanium into a film containing carbon as a main component.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：获得高记录密度和低功耗操作，并降低错误切换的可能性。解决方案：该非易失性半导体存储器包括电阻率根据电压或电流的施加而改变的电阻变化膜62，以及设置为将电阻变化膜62夹在其中的电极61和64 膜厚度方向。电阻变化膜62通过将从氢，硼，氮，氟，硅和钛中选出的至少一种附加元素溶解在含有碳作为主要成分的膜中而形成。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2011151077A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2011151077A
公开(公告)日：2011-08-04
申请号：JP2010009322
申请日：2010-01-19
申请人： Toshiba Corp , 株式会社東芝
发明人： TAKADA SHINTETSU , WATANABE KATSURA , OTSUKA KENICHI , KURASHIMA NOBUYUKI
IPC分类号： H01L21/304 , H01L21/3205 , H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, capable of suppressing erosion which occurs in a region of a high wiring density.
SOLUTION: The method of manufacturing a semiconductor device concerning one embodiment of this invention includes a process of forming wiring 8a and wiring 8b of a lower pattern density than that of the wiring 8a in a high density region 4a and a low density region 4b of a first insulating film 3, respectively, a process of lowering the height of the first insulating film 3 and exposing the upper parts 10a, 10b of the wiring 8a, 8b, a process of forming a second insulating film 11 covering the upper surface of the first insulating film 3 and the surface of the upper parts 10a, 10b such that the minimum height of the upper surface in the low density region 4b is lower than the height of the upper surfaces of the wiring 8a, 8b, a process of forming a third insulating film 12 on the second insulating film 11, and a process of grinding and flattening the third insulating film 12, the second insulating film 11 and the wiring 8a, 8b under the condition that each grinding rate of the wiring 8a, 8b and the third insulating film 12 is higher than the grinding rate of the second insulating film 11.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供能够抑制在高布线密度的区域中发生的侵蚀的半导体器件的制造方法。解决方案：关于本发明的一个实施例的制造半导体器件的方法包括在高密度区域4a和低密度区域中形成布线8a和布线8b的方法，该布线8a和布线8b的图案密度低于布线8a的图案密度 4b分别是使第一绝缘膜3的高度降低并使布线8a，8b的上部10a，10b露出的工序，形成覆盖上表面的第二绝缘膜11的工序第一绝缘膜3和上部10a，10b的表面，使得低密度区域4b中的上表面的最小高度低于布线8a，8b的上表面的高度，在第二绝缘膜11上形成第三绝缘膜12，在第三绝缘膜12，第二绝缘膜11和布线8a，8b的研磨和平坦化的过程中，在每个丝网的研磨速率 g 8a，8b和第三绝缘膜12比第二绝缘膜11的研磨速度高。版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2011124472A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2011124472A
公开(公告)日：2011-06-23
申请号：JP2009282621
申请日：2009-12-14
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAO SHINICHI , WATANABE KATSURA , TAKADA SHINTETSU , MASUDA HIDEAKI , OTSUKA KENICHI
IPC分类号： H01L23/52 , H01L21/3065 , H01L21/3205 , H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which reduces degradation of Cu wiring life, and degradation of an insulating property of an insulating film.
SOLUTION: The method of manufacturing a semiconductor device includes: a step (S102) of forming, on a chamber inner surface, a multilayer film using a silicon (Si) film as a surface layer; and a step (S106) of performing a rare gas plasma treatment by arranging a substrate formed with copper (Cu) wiring and the insulating film on a surface thereof in a chamber formed with the multilayer film on the inner surface.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种减少Cu布线寿命劣化以及绝缘膜绝缘性能降低的半导体器件的制造方法。解决方案：制造半导体器件的方法包括：在室内表面上形成使用硅（Si）膜作为表面层的多层膜的步骤（S102）; 以及通过将形成有铜（Cu）布线的基板和绝缘膜在其表面上形成有多层膜的室内布置来进行稀有气体等离子体处理的步骤（S106）。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2010283136A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010283136A
公开(公告)日：2010-12-16
申请号：JP2009135118
申请日：2009-06-04
申请人： Toshiba Corp , 株式会社東芝
发明人： MASUDA HIDEAKI , WATANABE KATSURA , OTSUKA KENICHI
IPC分类号： H01L21/318 , C23C14/06 , C23C16/42 , H01L21/768 , H01L23/522
CPC分类号： H01L21/02697 , H01L21/02074 , H01L21/02167 , H01L21/02274 , H01L21/02304 , H01L21/02312 , H01L21/3105 , H01L21/3148 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76883
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device for suppressing the transformation of a low dielectric insulating film upon removing the oxide film of the substrate of wiring. SOLUTION: The method of manufacturing the semiconductor device includes: a step of forming wiring 12 on the surface of an SiOC film 11 on a semiconductor substrate 10; a step of forming a fine layer 14 on the surface of the SiOC film 11 by exposing the SiOC film 11 on whose surface the wiring 12 has been formed to plasma containing noble gas or the mixed gas of the noble gas and N 2 gas; a step of removing an oxide film 13 formed on the surface of the wiring 12 after the fine layer 14 is formed; and a step of forming a diffusion prevention film 15 as an insulating film on the wiring 12 from which the oxide film 13 has been removed and the fine layer 14. The steps ranging from the removal of the oxide film 13 to the formation of the diffusion prevention film 15 are performed without being exposed to atmosphere. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，该半导体器件用于在去除衬底衬底的氧化物膜时抑制低介电绝缘膜的变换。解决方案：制造半导体器件的方法包括：在半导体衬底10上的SiOC膜11的表面上形成布线12的步骤; 通过将其上形成有布线12的表面的SiOC膜11暴露于含有惰性气体的等离子体或稀有气体和N 气体; 在形成微细层14之后除去形成在布线12的表面上的氧化膜13的步骤; 以及在除去氧化膜13的布线12上形成作为绝缘膜的防扩散膜15的步骤以及微细层14.从去除氧化膜13到形成扩散的步骤防止膜15在不暴露于大气的情况下进行。版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2011155074A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2011155074A
公开(公告)日：2011-08-11
申请号：JP2010014582
申请日：2010-01-26
申请人： Toshiba Corp , 株式会社東芝
发明人： TAKADA SHINTETSU , MASUDA HIDEAKI , WATANABE KATSURA , OTSUKA KENICHI
IPC分类号： H01L21/3205
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device in which no eaves shape is formed on an insulating film even if wet treatment is applied.
SOLUTION: The manufacturing method of a semiconductor device which is one embodiment includes a step (S102) for forming an insulating film on a substrate, a step (S104) for forming a protective film on the insulating film, a step (S114) for forming a first opening at the protective film, a step (S116) for forming a sacrifice film whose wet etching rate is higher than that of the protective film in the first opening, a step (part of S122) for forming a second opening whose width is narrower than that of the first opening at the sacrifice film in the first opening, a step (part of S122) for forming a third opening at the insulating film by transferring the second opening, a step (S126) for applying wet treatment after the third opening is formed, a step (S128) for forming a barrier metal film in the third opening after the wet treatment, and a step (S132) for embedding a conductive material in the third opening.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：为了提供即使使用湿处理也不会在绝缘膜上形成檐形状的半导体器件的制造方法。解决方案：作为一个实施例的半导体器件的制造方法包括用于在基板上形成绝缘膜的步骤（S102），在绝缘膜上形成保护膜的步骤（S104），步骤（S114 ），用于在所述保护膜上形成第一开口的步骤（S116），用于形成湿蚀刻速度高于所述第一开口中的保护膜的牺牲膜的工序（S116），形成第二开口其宽度比第一开口处的牺牲膜处的第一开口的宽度窄;通过转移第二开口在绝缘膜上形成第三开口的步骤（S122的一部分），用于施加湿处理的步骤（S126）在形成第三开口之后，在湿处理之后的第三开口中形成阻挡金属膜的步骤（S128）和用于在第三开口中嵌入导电材料的步骤（S132）。版权所有（C）2011，JPO＆INPIT

9. 发明专利

JP2010062242A Method of manufacturing semiconductor apparatus 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010062242A
公开(公告)日：2010-03-18
申请号：JP2008224538
申请日：2008-09-02
申请人： Toshiba Corp , 株式会社東芝
发明人： WATANABE KATSURA , OTSUKA KENICHI , KAWASE AKIFUMI
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L21/7682 , H01L21/76807 , H01L21/76832 , H01L21/76835
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor apparatus capable of preventing the entry of fluid or insulating materials into air gap, and suppressing the degradation of operation reliability and increase of electric capacitance.
SOLUTION: The method of manufacturing a semiconductor apparatus includes: a step of forming an interlayer sacrificial film in which a wiring is provided and an insulating film located on the interlayer sacrificial film on a semiconductor substrate having a semiconductor element; a step of etching the insulating film and the interlayer sacrificial film to form a groove reaching the interlayer sacrificial film; a step of forming a gas permeable film in the groove; a step of gasifying the interlayer sacrificial film and removing the gasified interlayer sacrificial film via the groove and the gas permeable film; and a step of forming a sealing film that seals proximity of an opening of the grove on the gas permeable film after removing the interlayer sacrificial film.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种能够防止流体或绝缘材料进入气隙的半导体装置的制造方法，并且抑制运行可靠性的劣化和电容的增加。解决方案：制造半导体装置的方法包括：在具有半导体元件的半导体衬底上形成设置有布线的层间牺牲膜和位于所述层间牺牲膜上的绝缘膜的步骤; 蚀刻绝缘膜和层间牺牲膜以形成到达层间牺牲膜的沟槽的步骤; 在槽中形成透气膜的工序; 气化所述层间牺牲膜并通过所述槽和所述透气膜去除所述气化的层间牺牲膜的步骤; 以及形成密封膜的步骤，所述密封膜在去除所述层间牺牲膜之后密封所述透气膜上的所述槽的开口的接近。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JPH07115130A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07115130A
公开(公告)日：1995-05-02
申请号：JP28061993
申请日：1993-10-14
申请人： TOSHIBA CORP
发明人： TAKAHASHI MARI , KITAKURA TOMONORI , OTSUKA KENICHI , MORI SHIGEYA
IPC分类号： H01L21/768
摘要： PURPOSE:To provide a method of manufacturing a semiconductor device, wherein plug material such as tungsten or the like is hardly deposited on a part other than a contact hole and is filled into the contact hole excellent in selectivity at high-temperature deposition. CONSTITUTION:A first wiring 8 of polysilicon or the like is formed on a silicon semiconductor substrate 1 through the intermediary of an insulating film 7, and an interlayer insulating film 9 provided with a contact hole 10 is farmed covering the first wiring 8 on the insulating film 7 and flattened. A natural oxide film 11 formed on the surface of the first wiring 8 exposed at the inner base of the contact hole 10 is removed by plasma etching with halogen gas or the like. Thereafter, the semiconductor substrate 1 is exposed to gas which contains halogen such as F2 cur the like for 10 to 50 seconds at a room temperature to a temperature of 400 deg.C. As halogen is attached to the inner wall of the contact hole and the surface of the insulating film 9, plug material which is selectively grown inside the contact hole in art after process is hardly attached onto the insulating film 9.

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